ASIC_int
Advanced Member level 4
FVMI fear, I'm getting tired of contradicting this assumption. Synthesis does take care of. This way, synthesis results are consistent with simulation.
The statement was written to std_match on his context and not to you. I did not wrote that synthesis does not take care of bloking nature of verilog. I agree that synthesis does not take care of bloking nature of verilog.
---------- Post added at 15:48 ---------- Previous post was at 15:44 ----------
std_match
I think you are completely wrong in understanding the essence of this discussion and that is resulting in you stating "This is why I say you don't understand blocking/non-blocking for combinatorial logic." I write in the earlier post that I understand blocking/non-blocking for combinatorial logic as far as you want others to know. However u could not provide more knowlede on it.
I think you are in the last making useless discussion irrelavant to the topic.