Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

question about source follower circuit

Status
Not open for further replies.
jimito13

jimito13

Advanced Member level 1
Joined
Nov 17, 2008
Messages
464
Helped
130
Reputation
262
Reaction score
113
Trophy points
1,323
Location
Greece
Activity points
4,929
Hello all,

I am designing a nmos source follower circuit to use it both as buffer and level shifter in my design.A long time ago a colleague had told me that for this circuit a lot of bias current is needed for good linearity but he didn't explain me further...Now,i need this info!Can somebody explain me this with some equations or some references that give a proof?

And another question.As an alternative buffer topology except from an opamp with high low-freq. gain connected as unity gain amplifier,is there any other topology that can be used for this purpose?

Any helpful answer or other kind of source would be appreciated.

Best Regards,
Jimito13
 

If you need high linearity, low noise amplifier use the source follower in a deep nwell. You can thus connect source and bulk together hence perfect linearity, no substrate noise. Cost: larger area
 

I am aware of this technique adix but i am seeking an answer about the bias current...Thanks in any case for your answer.
 

Refer to any text to find the small signal gain of a source follower.
You will find a gmRs term in the numerator, and depending on your configuration, a sum of gm, gmb, gds and 1/Rs terms in the denominator.
We ideally want to gain to be 1 for linearity. To achieve that
1. You remove gmb by shorting the body and source.
2. You would want as large a gm as possible. This means using a large biasing current, or using a very large MOS.
 
checkmate said:
We ideally want to gain to be 1 for linearity.
.........
2. You would want as large a gm as possible. This means using a large biasing current, or using a very large MOS.
Click to expand...

*The gain never can reach unity - however, if you are lucky, rather close to it.
* "Biasing current" for a MOSFET?
 

LvW said:
*The gain never can reach unity - however, if you are lucky, rather close to it.
* "Biasing current" for a MOSFET?
Click to expand...
Did I write anything wrong? Please enlighten me.
 

Yes i already know the equation that gives the low-freq. gain of the source follower...Ok,now i understand that for large gm to approach gain=1 we need large dc currect for the nmos.

Has this bias current any relationship with the load seen at the output of the buffer?That is if we have load with small impedance we need large bias current for the buffer?
 

checkmate said:
Did I write anything wrong? Please enlighten me.
Click to expand...

Hi checkmate, may be there was a misunderstanding. To me "biasing" means to provide the control pin of a transistor with a "bias current" or a "bias voltage" (examples: base current, gate voltage). But I realize that you were referring to the drain current as "bias condition". Sorry.
LvW
 

LvW said:
Hi checkmate, may be there was a misunderstanding. To me "biasing" means to provide the control pin of a transistor with a "bias current" or a "bias voltage" (examples: base current, gate voltage). But I realize that you were referring to the drain current as "bias condition". Sorry.
LvW
Click to expand...

It's okay. To me, to bias a transistor is to set the operating point of the transistor.
Sometimes we do it with a gate voltage, ie current mirrors.
Sometimes we do it with a drain current, ie input/output stages.
Granted a lot of texts often use the "bias" word all over the place but not give an explicit definition of it. I once also had to grapple with this ambiguity over the definition of bias.
 

checkmate said:
It's okay.
To me, to bias a transistor is to set the operating point of the transistor.
............
Click to expand...

Can I view this as consent? Also to me "biasing" means to set the operating point (e.g. with a proper gate voltage) rather than the operating point itself. But forget this objection - it is more or less philosophy of wordings (I am even not sure about the correctness of my "wording").
Regards
LvW
 

Has this bias current any relationship with the load seen at the output of the buffer?That is if we have load with small impedance we need large bias current for the buffer?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top