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uart in spartan 3an (vhdl)

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Pravinspidy

Pravinspidy

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hi..

guys did any one tried vhdl code in spartan 3an... i want to implement a uart communication in it.... so please any one help me too develop the code for dis case....:cool:
 

I am currently using this one, it's very small and quite simple. It's code is somewhat ugly IMHO, but it works OK.

Oops, sorry, it's Verilog, not VHDL. But I can provide a VHDL instantiation code if that will help you.
There are 2 or 3 UARTs at opencores that I haven't tried yet. I'll report back here if I find one of those better than the one I mentioned here.
 
To use that UART you must declare a component in your module:

Code VHDL - [expand]
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component uart_transceiver is 
    port(
    sys_rst: in std_logic;
    sys_clk: in std_logic;
 
    uart_rx : in    std_logic;
    uart_tx : out   std_logic;
 
    divisor : in std_logic_vector(15 downto 0);
 
    rx_data : out   std_logic_vector(7 downto 0);
    rx_done: out    std_logic;
    rx_bsy: out std_logic;
 
    tx_data : in    std_logic_vector(7 downto 0);
    tx_wr : in  std_logic;
    tx_done: out    std_logic
);
end component;


The interface is pretty obvious except for divisor. It's a parameter of a baud rate generator, and it's not documented, so I had to guess. For 115 200 baud and 50 MHz clock it's x"001B".
 

Alexium said:
To use that UART you must declare a component in your module:

Code VHDL - [expand]
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component uart_transceiver is 
    port(
    sys_rst: in std_logic;
    sys_clk: in std_logic;
 
    uart_rx : in    std_logic;
    uart_tx : out   std_logic;
 
    divisor : in std_logic_vector(15 downto 0);
 
    rx_data : out   std_logic_vector(7 downto 0);
    rx_done: out    std_logic;
    rx_bsy: out std_logic;
 
    tx_data : in    std_logic_vector(7 downto 0);
    tx_wr : in  std_logic;
    tx_done: out    std_logic
);
end component;


The interface is pretty obvious except for divisor. It's a parameter of a baud rate generator, and it's not documented, so I had to guess. For 115 200 baud and 50 MHz clock it's x"001B".
Click to expand...

hi, thanks a lot can u give the full code for this so that i can understand easily..........
 

Alexium said:
For 115 200 baud and 50 MHz clock it's x"001B".
Click to expand...
Actually, it's clk frequency / 16 / desired baud rate (rounded to nearest integer, I guess).

---------- Post added at 13:55 ---------- Previous post was at 13:53 ----------
Pravinspidy said:
hi, thanks a lot can u give the full code for this so that i can understand easily..........
Click to expand...
What code would yo like to see, specifically? Port map, or something else? I'm not sure my code will help you much...
 

ya i need port map coz i am using spartan 3an starter kit ..... so i jus want do serial communication with pc
 

OK, this is how I've tested it:

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity RS232_test is
    Port ( clk_50MHz : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           RS232_rx : in  STD_LOGIC;
           RS232_tx : out  STD_LOGIC;
           LED : out  STD_LOGIC_VECTOR (7 downto 0));
end RS232_test;
 
architecture Behavioral of RS232_test is
 
component uart_transceiver is 
    port(
    sys_rst: in std_logic;
    sys_clk: in std_logic;
 
    uart_rx : in    std_logic;
    uart_tx : out   std_logic;
 
    divisor : in std_logic_vector(15 downto 0);
 
    rx_data : out   std_logic_vector(7 downto 0);
    rx_done: out    std_logic;
    rx_bsy: out std_logic;
 
    tx_data : in    std_logic_vector(7 downto 0);
    tx_wr : in  std_logic;
    tx_done: out    std_logic
);
end component;
 
signal RXByte,TXByte, debug: std_logic_vector(7 downto 0);
signal tx_req:  std_logic;
signal tx_end:  std_logic;
signal rx_ready,rx_busy:    std_logic;
 
type stateType is (receiving, transmitting);
signal state: stateType;
begin
    
RS232: uart_transceiver  
    port map (
    sys_rst => rst,
    sys_clk => clk_50MHZ,
 
    uart_rx => RS232_rx,
    uart_tx => RS232_tx,
 
    divisor => x"001B",
 
    rx_data => RXByte,
    rx_done => rx_ready,
    rx_bsy => rx_busy,
 
    tx_data => TXByte,
    tx_wr => tx_req,
    tx_done => tx_end
);
    
Mirror: process (clk_50MHz, rst)
begin
    if rst = '1' then
        TXByte <= x"01";
        state <= receiving;
        tx_req <= '0';
    elsif rising_edge(clk_50MHz) then
        case state is
        when receiving =>
            if rx_ready = '1' then 
                state <= transmitting;
                TXByte <= RXByte;
                LED <= RXByte;
                tx_req <= '1';
            end if;
        when transmitting =>
            tx_req <= '0';
            if tx_end = '1' then
                state <= receiving;
            end if;
        end case;
    end if;
end process;    
    
end architecture;


The code transmits back every received byte.
 
hi,,,, syntax is ok but iam getting error in translate

---------- Post added at 11:10 ---------- Previous post was at 10:38 ----------

hi think dis may create problem think so................

---------- Post added at 11:13 ---------- Previous post was at 11:10 ----------

hi,, dis is synthesis report

Reading design: RS232_test.prj

=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "D:/Xilinx/labview/RS232_test/RS232_test.vhd" in Library work.
Architecture behavioral of Entity rs232_test is up to date.

=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <RS232_test> in library <work> (architecture <behavioral>).


=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <RS232_test> in library <work> (Architecture <behavioral>).
WARNING:Xst:2211 - "D:/Xilinx/labview/RS232_test/RS232_test.vhd" line 69: Instantiating black box module <uart_transceiver>.
Entity <RS232_test> analyzed. Unit <RS232_test> generated.


=========================================================================
* HDL Synthesis *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <RS232_test>.
Related source file is "D:/Xilinx/labview/RS232_test/RS232_test.vhd".
WARNING:Xst:646 - Signal <rx_busy> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <debug> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Found 8-bit register for signal <LED>.
Found 1-bit register for signal <state<0>>.
Found 1-bit register for signal <tx_req>.
Found 8-bit register for signal <TXByte>.
Summary:
inferred 10 D-type flip-flop(s).
Unit <RS232_test> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers : 4
1-bit register : 2
8-bit register : 2

=========================================================================

=========================================================================
* Advanced HDL Synthesis *
=========================================================================

Loading device for application Rf_Device from file '3s700a.nph' in environment D:\xilinx10\ISE.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Registers : 18
Flip-Flops : 18

=========================================================================

=========================================================================
* Low Level Synthesis *
=========================================================================

Optimizing unit <RS232_test> ...

Mapping all equations...
WARNING:Xst:2036 - Inserting OBUF on port <RS232_tx> driven by black box <uart_transceiver>. Possible simulation mismatch.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block RS232_test, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers : 18
Flip-Flops : 18

=========================================================================

=========================================================================
* Partition Report *
=========================================================================

Partition Implementation Status
-------------------------------

No Partitions were found in this design.

-------------------------------

=========================================================================
* Final Report *
=========================================================================

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk_50MHz | BUFGP | 18 |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------+------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
rst | IBUF | 10 |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

Minimum period: 2.970ns (Maximum Frequency: 336.700MHz)
Minimum input arrival time before clock: 3.642ns
Maximum output required time after clock: 5.531ns
Maximum combinational path delay: 4.940ns

=========================================================================

Process "Synthesis" completed successfully

---------- Post added at 11:20 ---------- Previous post was at 11:13 ----------

this is the translate report...

Command Line: D:\xilinx10\ISE\bin\nt\unwrapped\ngdbuild.exe -ise
D:/Xilinx/labview/RS232_test/RS232_test.ise -intstyle ise -dd _ngo -nt timestamp
-i -p xc3s700an-fgg484-4 RS232_test.ngc RS232_test.ngd

Reading NGO file "D:/Xilinx/labview/RS232_test/RS232_test.ngc" ...
Reading in constraint information from 'RS232_test.ucf'...
Gathering constraint information from source properties...
Done.

Resolving constraint associations...
Checking Constraint Associations...
Done...
Checking Partitions ...

Checking expanded design ...
ERROR:NgdBuild:604 - logical block 'RS232' with type 'uart_transceiver' could
not be resolved. A pin name misspelling can cause this, a missing edif or ngc
file, or the misspelling of a type name. Symbol 'uart_transceiver' is not
supported in target 'spartan3a'.

Partition Implementation Status
-------------------------------

No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
Number of errors: 1
Number of warnings: 0


One or more errors were found during NGDBUILD. No NGD file will be written.

Writing NGDBUILD log file "RS232_test.bld"...

Process "Translate" failed
Compiling vhdl file "D:/Xilinx/labview/RS232_test/RS232_test.vhd" in Library work.
Entity <RS232_test> compiled.
Entity <RS232_test> (Architecture <Behavioral>) compiled.
No DRC error found.
 

hi,
Alexium

thanks thanks a lot its working fine,,, i have tested ur code......................... once again thanks... cheers!!!!!!!!!!
 

hi one more the uart_transceiver.zip u have sent is a verilog file i think ... can u please give vhdl file for it ... if so it will be helpfull.. now i can able to understand the code little .... still learning.... thanks in advance
 

No, I only tried this verilog module. There are VHDL UARTs at opencores, but like I said, some of those I didn't try and others I didn't like. I've also written my very own UART in VHDL, but couldn't get it working for some reason. I'm just learning, too...
 
k... thank you i revert u back if any clarification........ & also i like to keep in touch with u.... i am now learning vhdl... can u help me ..??... i am a embedded engineer know to write code in microcontrollers & labview based projects..... i have done a simple code in vhdl.... long time before... nw i am back to fpga for communicating .... labview & fpga via serial port.....
 

Alexium said:
To use that UART you must declare a component in your module:

Code VHDL - [expand]
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component uart_transceiver is 
    port(
    sys_rst: in std_logic;
    sys_clk: in std_logic;
 
    uart_rx : in    std_logic;
    uart_tx : out   std_logic;
 
    divisor : in std_logic_vector(15 downto 0);
 
    rx_data : out   std_logic_vector(7 downto 0);
    rx_done: out    std_logic;
    rx_bsy: out std_logic;
 
    tx_data : in    std_logic_vector(7 downto 0);
    tx_wr : in  std_logic;
    tx_done: out    std_logic
);
end component;


The interface is pretty obvious except for divisor. It's a parameter of a baud rate generator, and it's not documented, so I had to guess. For 115 200 baud and 50 MHz clock it's x"001B".
Click to expand...
can u plz post the complete code with test bench
 

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