(error) illegal left hand site of continous assign.......

my program is to add IEEE754 single precision number.......
it show the error said that........
-Reference to vector reg 'r' is not a legal net lvalue
-Illegal left hand side of continuous assign

...........................................here is my code..............................

module fadd3(
input clk,
input [31:0] a,
input [31:0] b,
output reg [31:0] r
);

wire sa;
wire [7:0] ea;
wire [22:0] fa;
assign sa = a[31];
assign ea = a[30:23];
assign fa = a[22:0];

wire sb;
wire [7:0] eb;
wire [22:0] fb;
assign sb = b[31];
assign eb = b[30:23];
assign fb = b[22:0];

/* Stage 1
* Sort the numbers according to the exponent.
* A becomes the number with the biggest exponent.
* Negate b in case of substraction.
*/

reg sa1;
reg [7:0] eL;
reg [22:0] fracL;
reg sb1;
reg [7:0] eS;
reg [22:0] fracS;

always @(posedge clk) begin
if(ea > eb) begin
sa1 <= sa;
eL <= ea;
fracL <= fa;
sb1 <= sb;
eS <= eb;
fracS <= fb;
end else begin
sa1 <= sa;
eL <= eb;
fracL <= fb;
sb1 <= sb;
eS <= ea;
fracS <= fa;
end
end

/* Stage 2
* Add leading (integer) bits on the mantissas.
* Compute the difference between the exponents.
*/

reg [7:0] diff;
reg sa2;
reg [7:0] ea2;
reg [23:0] fa2;
reg sb2;
reg [23:0] fb2;
reg [7:0] eb2;
always @(posedge clk) begin
diff <= eL - eS;

sa2 <= sa1;
sb2 <= sb1;
eb2 <= eL;
fb2 <= fracS;

end

/*stage 3*/

reg [22:0] fr;
reg [22:0] fracr;
reg [7:0] er;
reg sr;

always @(posedge clk) begin

fr <= {(1+fracS)};
fracr <= fr>>diff;
er <= eb2;
sr <= sb2;
end

assign r[31] = sr;
assign r[30:23] = er;
assign r[22:0] = fracr;

endmodule

..................................................................................

could anyone tell me how to correct the error

You didn't define wire 'r' anywhere...

r.b.

r is a register so you can't use 'assign'

you can use

always @*
begin
r[31] = sr;
r[30:23] = er;
r[22:0] = fracr;
end

Sorry, I didn't see r was defined as a register in the port list.


Alternatively declare 'r' as a wire.

r.b.