RF Drive amplifier and its current density

I have a RF drive amplifier and I'm using TSMC 0.9nm NMOS_RF for it. It has 12 fingering with 2.5um for each finger. The transistor has roughly 2mA going through it.

I checked my transistor layout provided by the PDK, and it shows that each fingering diffustion area has metal1(including contact) width of .14um . Since it is it has 12 fingering, this gives roughly .14um*6=.84um of metal width at the drain and source node to carry the 2mA. This falls short of the 1mA/um current density rule that we use as rule of thumb.

Do I have to increase the diffusion area and increase metal1 width? I'm thinking that this is the right solution, but it will cause tremendous amount of rework. not fun!

Can I just ignore current density problem and move on? Will it absolutely cause a problem? Or is it just more of a reliability problem that can go undetected for research purpose ICs.
let me know

Your current density rule is predicated on some maximum temp,
service factor and lifetime required. For me, that's 125C, 100%,
10 years. Somebody making a singing Christmas card chip might
be a little less demanding.

With such short fingers and already violating current density,
you may want to look more closely at power density and self
heating as well.

You could consider taking the current out vertically (vias to
a Met2 or higher comb) so that Met1 width is not the constraint.
You can have a high fill factor at higher levels and you can do
taper structures and space FET cells apart without capacitance
penalty in higher-power structures. Using your top, thick metal
layer would be a good idea for a power amp (as well as minimizing
substrate capacitance, at the cost of all those vias' resistance).

Given that power density is a likely issue, you might elect to not
make the FET a minimum-minimum-minimum device but use
(say) a 2xN source and drain region shared, getting at least 2X
the metal width. Yes, this adds S/D bottom plate area.

Thank you. that was extremely helpful...
Basically, in a nut shell, the current density rule has to do with chip reliability, and if we don't need it to be as robust as market products, then we can afford to pay less attention to it

I'm a little confused with what you mean by power density? How is it different from current density?
According to your fourth paragraph, basically I should just increase the diffusion area to increase metal width right?
I thought that implementing it the way you mentioned in your third paragraph would be suffice.... no?

Current density is about metal migration over the long term.

Power density sets up a local heat rise in the channel and
other dissipative elements. At higher temps your body resistance
and parasitic BJT beta both rise, potentially leading to a turnon
and single transistor latch / thermal runaway. In thin film SOI
it may just be a fuse. Calculating thermal rise from a point
"heater" is kind of tricky, and a collection of them, maybe
intractable without finite element tools.

Another option to consider is making the device be fed from
both ends. That is, use (say) met2 straps to distribute top
level S/D, parallel stripes, and via down to both ends of each
local S, D stripe (staggered tabs). This will halve your end-
of-finger current density, and additionally may help debiasing.