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Timing Issues_DDR3 SDRAM

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Ramesh_SI

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Hi,

I am performing DDR3 Signal Integrity analysis.I noticed timing margin changes with change in ODT.I would like o know the relation between DDR ODT and Timing.Thanks in advance.
 

Sorry, I can only suggest checking "Altera; External Memory Interface Handbook Volume 2" Section II, Board Planning - I'm looking at Dec.2010 publication. Pages 2-5 and 2-6 may help...good luck.

Sorry - new here, should be able to attach link...
 
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