Semiconductor (manufacoring) technology questions

Semiconductor (manufactoring) technology questions

Hi, I've got some questions on semiconductor technology. It would be nice if you could help me here. I know they look random - that's because most of them are already answered, or I found answers myself

1) Could you suggest any good books on optics for lithography? All these aspherical lenses, phase correctness, quadruple illumination, high-NA optics, immersion optics - that kind of things...
2) In production - does every PECVD chamber use only 1 chemical? I.e. 1 chamber per each processing step using different plasma formula. Or there is no much contamination when changing gases?
3) Are there any (hopefully) free software for single transistor simulation (so that you can play with gate oxide for example and see how it works)?
4) Could you suggest what's the differentce in shottky barriers with Si doped to n/p?
5) Could you suggest is that possible to find detailed process descriptions & libraries for 0.5-1um CMOS/NMOS(logic, no HV) processes?
6) What is practical limit for contamination which makes transistors not usable at all? I.e. parameters surely degrade, but I wonder when it's stops working at all. For example a-Si:H transistors are terrible, but we use them - so probably dirty silicon is also somewhat useful.
7) Is that correct that the disadvantages of Ag/Au metallization are the following:
7.Ag: Chemically active, requires interface to Si.
7.Au: Intermetallic compounds with Si formed even at 300C, which is below temperatures used in general ASIC processes.

8 ) Why Si oxidation by HNO3 is not generally used? I doubt everyone love heating things to 1100C...

I don't need answers for everything at once If you can answer 1 or 2 that would be great

3) I heard Sentaurus or tsuprem+Medici can be used for device simulation.

For 3, if you go to Linear Technology - Linear Home Page you can download LTCspice. It is the exact software the company using in house but with No layout options. You will have to find another way to layout. For 5, then just go to the MOSIS Integrated Circuit Fabrication Service website you can download your tech file then include and simulate in LTCspice. Then change your Tox values or whatever you want to do!
Jgk

leo_o2 said:

3) I heard Sentaurus or tsuprem+Medici can be used for device simulation.

Click to expand...

Seems that both are around Synopsis TCAD which defenetly can do the job, but very far from being available to me (from the price prospective).

---------- Post added at 11:20 ---------- Previous post was at 11:12 ----------

jgk2004 said:

For 3, if you go to Linear Technology - Linear Home Page you can download LTCspice. It is the exact software the company using in house but with No layout options. You will have to find another way to layout. For 5, then just go to the MOSIS Integrated Circuit Fabrication Service website you can download your tech file then include and simulate in LTCspice. Then change your Tox values or whatever you want to do!
Jgk

Click to expand...

3) Well LTCspice is on higher level. I was looking at something which is able to physically simulate processes on single transistor and extract it's parameters based on physical specifications.

5) MOSIS does not have "obsolete" processes. They all are more or less recent (biggest one is 0.7um but it's HV). I do not want to just run LTCspice simulation - I want to be able to perform complete design down to masks for specific process and simulate it on low level. That's why I need the process details & decent production-grade libraries. I understand that chances of obtaining this info for <0.2um process without NDA are slim, hence the reason I am asking for obsolete process.

1) Could you suggest any good books on optics for lithography? All these aspherical lenses, phase correctness, quadruple illumination, high-NA optics, immersion optics - that kind of things...

Do not know any good books that cover this subject for IC Fabrication but there are plenty of IEEE (etc) papers if you can get hold of them.

2) In production - does every PECVD chamber use only 1 chemical? I.e. 1 chamber per each processing step using different plasma formula. Or there is no much contamination when changing gases?

In PECVD there may be up to 4 gases per chamber. For example a TEOS chamber will be plumbed with O2, TEOS, C2F6 an SION chamber will have SiH4, N2O, O2, PH3. In general chambers are dedicated so TEOS would be dedicated to TEOS only, SION may be used for SION and Si3N4, etc, etc. You may have 4 chambers per platform so chamber could be mixed within 1 platform.
So if you final passivation process was TEOS followed by SiON, one platform with different chamber could be used so the wafer never breaks vacuum between the TEOS deposition and the Si Oxy Nitride deposition.

3) Are there any (hopefully) free software for single transistor simulation (so that you can play with gate oxide for example and see how it works)?

Yes. Find and download Pisces2B and Suprem4. These are available to compile in Linux -but you need fortran (g77 or gfortran) and gcc
There are however, windows versions of these pre-compiled (ready to run):

For PISCES2B (2D device simulator) h**p://home.comcast.net/~john.faricelli/tcad.htm.
For SupremIV I dont know where the binary is any more but can send a copy to you.

They are not easy to use but there would be plenty of help from people in this forum.

4) Could you suggest what's the differentce in shottky barriers with Si doped to n/p?

The forward voltage is lower for a schottky diode than a PN or NP diode so the voltage drop across the diode is smaller. This makes it very useful in voltage charge pumps and buck/boost convertors where you want to minimise any voltage drops which harm efficiency.

5) Could you suggest is that possible to find detailed process descriptions & libraries for 0.5-1um CMOS/NMOS(logic, no HV) processes?

Detailed Process descriptions are hard to come by as they are proprietary. If it is just for learning (TCAD) then again ask specifics here are you will probably get what you want. For libraries useful for Spice simulation check out MOSIS.

6) What is practical limit for contamination which makes transistors not usable at all? I.e. parameters surely degrade, but I wonder when it's stops working at all. For example a-Si:H transistors are terrible, but we use them - so probably dirty silicon is also somewhat useful.

Huge subject. For example an aluminium suface contamination level of 1E11 atoms/cm3 on an SRAM can couse issues at low temperature where the SRAM develops stuck bits. Carbon and other contaminants in DI Water can cause gate oxides to fail under stress.

7) Is that correct that the disadvantages of Ag/Au metallization are the following:
7.Ag: Chemically active, requires interface to Si.
7.Au: Intermetallic compounds with Si formed even at 300C, which is below temperatures used in general ASIC processes.

Yes. But both are used in backend processes after the wafer has been completed prior to packaging.

8 ) Why Si oxidation by HNO3 is not generally used? I doubt everyone love heating things to 1100C...

Nitrogen incorporation into the oxide can enhance breakdown performance but degrate noise.

Thanks for the awesome answers

Colbhaidh said:

4) Could you suggest what's the differentce in shottky barriers with Si doped to n/p?

The forward voltage is lower for a schottky diode than a PN or NP diode so the voltage drop across the diode is smaller. This makes it very useful in voltage charge pumps and buck/boost convertors where you want to minimise any voltage drops which harm efficiency.

Click to expand...

These are advantages of schottky diode over usual PN one. I am in interested how does behavior of Schottky diode change if we dope the semiconductor to P or N?

Colbhaidh said:

5) Could you suggest is that possible to find detailed process descriptions & libraries for 0.5-1um CMOS/NMOS(logic, no HV) processes?

Detailed Process descriptions are hard to come by as they are proprietary. If it is just for learning (TCAD) then again ask specifics here are you will probably get what you want. For libraries useful for Spice simulation check out MOSIS.

Click to expand...

It is understandable that they are proprietary. But 1um processes are obsolete 20 years ago, and they still not available? Unfortunately, Spice simulation is not enough. My final goal is to be able to make a working couple of transistors on a wafer in a lab - and while all steps are more or less clear, outdated process description would really help me save a lot of time & trials.

Colbhaidh said:

6) What is practical limit for contamination which makes transistors not usable at all? I.e. parameters surely degrade, but I wonder when it's stops working at all. For example a-Si:H transistors are terrible, but we use them - so probably dirty silicon is also somewhat useful.

Huge subject. For example an aluminium suface contamination level of 1E11 atoms/cm3 on an SRAM can couse issues at low temperature where the SRAM develops stuck bits. Carbon and other contaminants in DI Water can cause gate oxides to fail under stress.

Click to expand...

I see, very interesting. Are there any good books on this subject? Everything I see in books/ebooks does not focus on contamination issues beyond "It's all need to be ultrapure".

Colbhaidh said:

8 ) Why Si oxidation by HNO3 is not generally used? I doubt everyone love heating things to 1100C...

Nitrogen incorporation into the oxide can enhance breakdown performance but degrate noise.

Click to expand...

I see, shouldn't be an issue for digital ASICs yet. I wonder if SiO2 quality is ok for gate dielectric and why it's not used...

Just realized that TCAD is a general word, not just Synopsys TCAD :-D

This looks so juicy.. I feel sooo poor now
**broken link removed**

9) How far are Synopsys T-CAD simulation results from reality? Specifically, how far extracted transistors parameters are from manufactured ones when T-CAD simulation is set for this specific technology?

Re: Semiconductor (manufactoring) technology questions

BarsMonster said:

1) Could you suggest any good books on optics for lithography? All these aspherical lenses, phase correctness, quadruple illumination, high-NA optics, immersion optics - that kind of things...

Click to expand...

Amazon.com: Fundamental Principles of Optical Lithography: The Science of Microfabrication (9780470727300): Chris Mack: Books

also: Chris Mack, Gentleman Scientist

BarsMonster said:

3) Are there any (hopefully) free software for single transistor simulation (so that you can play with gate oxide for example and see how it works)?

Click to expand...

Ports of TCAD Software to Win32 and Linux

BarsMonster said:

4) Could you suggest what's the differentce in shottky barriers with Si doped to n/p?

Click to expand...

kT/e*ln(N*P/ni^2) - which is about a bandgap in Silicon (~1.0V) - this is equal to he difference of Fermi levels in p-type and n-type doped Si.

BarsMonster said:

9) How far are Synopsys T-CAD simulation results from reality? Specifically, how far extracted transistors parameters are from manufactured ones when T-CAD simulation is set for this specific technology?

Click to expand...

TCAD simulation is a mutli-parameter and multi-dimensional problem. It may require "calibration", i.e. fitting some of the parameters (even fundamental parameters - such as workfunction of the gate material) in order to get a good match between simulations and measurements. TCAD simulations may capture some trends and miss some other trends. Some of the trends cannot be predicted with TCAD at all. The problem is exacerbated by the fact that there are a huge number of fitting or tuning parameters, especially for process simulations (as opposed to device simulations), most of them are not known precisely and have to be "tuned".

Typically when a foundry is designing a new process - say we want a 32nm process when we have a stable 45nm.
Market research will dictate the rough requirements for the transistors (cost of wafer (process), threshold voltage, leakage and drive currents, passive component needs etc.)
The Device Physics group will come up with the transistor design (FINFET, stretched Si, blah de blah...) and use TCAD to prove the concept. Once the concept is agreed, the road map will dictate a heavy TCAD effort to produce the Fab process that will be used. Since this TCAD will be calibrated to the Fab (implant profiles calibrated against actual silicon implants using SIMS, diffusions similarly calibrated, etc) then the TCAD for the new process will be expected to be within 10-30% of what will be the actual performance.
From the finished (rev0) TCAD, spice models can be extracted allowing design to go ahead and start on the technology development vehicle (SRAM or something) and process integration to design test structures for the first reticle set for the new process. This will be a R&D mask set only.
This will run through the fab and then measured when finished. The results will then be used to optimise (ie fix) TCAD and allow extraction of rev1 spice parameters for design.
If required there may be a second round of R&D Silicon should something have gone wrong or TCAD was way off.
Anyway once the process is qualified, TCAD should be within 10% of actual silicon if proper 3D was used.

Still looking for more information about

a) how contamination affect FET/BJT transistor parameters....
Any links/books?

And

b) Why Si oxidation by HNO3 is not generally used?.

Still actual

In response to (b): a common oxidation ambient is H2+O2+N2 and HCl+O2+N2. HNO3 is not common as it is easier to purify the individual gases and supply them to the furnace independently allowing varying mixtures of each gas. During the very pure phase of oxidation, there is no nitrogen, just O2 and H2 or O2 and HCL or just O2 for reasons I gave earlier - you do not always want nitrogen in the oxide.

For contamination effects, they are too numerous to list.

Common contaminants are Fe in the si crystal causing deep trap sites, Aluminium surface contamination causing non uniform oxide growth. These can come from the packaging matrials (plastics) used to transport chemical used in wafer processing, or erosion of components exposed to extreme pH's during chemical processing such as thermocouples, pH monitors, pumps etc.
They can also come from electrodes in plasma systems when their p[rotection (eg anodisation) breaks down through wear out, sputtering contaminants onto the wafer surface.
Carbon, which can cause any of the above coming from micro organisms in the hyper pure water used during wafer processing
Mobile ions like sodium and potassium, which can move under temperature & voltage stress then cause fixed positive charges. In a gate oxide,, this can cause uncontrolled variations in threshold voltage. These can come from human contamination and (more in the past) chemical mechanical polishing.
Oxygen precipitates from the manufacture of the bare Si wafer can cause crystal faults which if close to the surface, or propagate damage towards the surface can lead to leakages as faults cross PN juctions. This can also come from stresses caused by implantation itself. Bron implants tend to shrink the lattice, arsenic and Antimony expand the lattice either can cause stresses to form eventually causing faults.
Implantes can also cross contaminate. An implater used for Boron implantation, then used for Arsenic, may carry boron contamionation in the beam causing unexpected species contamination in the implanted region. The implanter liquid sources used to be housed in presuurised bottles coated with tungsten. This tungsten could find its way onto the wafer as a contaminant.
Where plasma systems use polymerisation to enable RIE etching (vertical sidewalls), the polymer also forms all over the inside of the plasma chamber. This polymer would be rich in the etchant species (eg flourine) which could then be released in subsequent processes that used the same chamber. A common fault this causes is where the final aluminium pad is exposed by etching windows in the passivation (using a flourine plasma). The fluorine contaminant finds it way onto the surface of the exposed aluminium pad to be used for bonding wires. During backside grinding of the wafer before assembly, the aluminium pads are exposed to water releasing the flourine which then etches the aluminium causing bonding failure.
Even the foam used to pack wafers to ship them to assembly causing contamination issues as the foam contained flourine!!

I dont know of any books on the subject but could probably write several hundred on the subject. But you would need to be really sad to read them!

Colbhaidh said:

But you would need to be really sad to read them!

Click to expand...

Wonder how they still can produce working chips! ;-)
SCNR

A Fab will have a defectivity group consisting of very experienced engineers. This group is typically quite large (10 people or more).
The fab have point of use analysis tools that sample chemicals, exhaust gases from plasma etchers, air borne particles etc
They will have inspectiuon systems using lasers to detect particles on the wafer surfaces down to 0.1um in size. They will use special inspection systems that look at two adjacent devices on a wafer, compare the video images of both in 5umx5um blocks pixel by pixel. Any difference is flagged as a defect. Electron microscopes are used 24/7 analysing any defects found.
If you ever have watched CSI, then most fabs are 5-10 years ahead of state of the art criminal forensics.

Colbhaidh said:

....
Even the foam used to pack wafers to ship them to assembly causing contamination issues as the foam contained flourine!!

I dont know of any books on the subject but could probably write several hundred on the subject. But you would need to be really sad to read them!

Click to expand...

That was very useful response, and I am ready to be sad
I am especially interested in impurity levels tolerance for non-state of art CMOS/BJT processes (0.25-0.5um)

Still looking for information about how contaminations affect parameters & long-term stability.

Still actual

I need some advice. If we have say stuck bits issue on an SRAM, and xSEM shows gate oxide pin hole defects - what are the things to look out for?