ZBT SRAM on virtex 5?

Hi
I am trying to use ZBT Synchronous SRAM on the ml501 virtex 5 board. Where can I get a tutorial on how to use it. For example I can not connect the output and input pins of the FPGA to the input and output pins of ZBT. I need to know how to configure/identify the pins.

Sorry for reviving an older thread. I just found this post and I thought I could provide some insight to an area that I am also having trouble getting to work correctly. Hopefully it will provide assistance to some one facing a similar issue.

The attached file includes a ucf location constraints file for the ML501 V5LX50T. Timing constraints need to be added. I searched for UCF for ML501 on Xilinx and it appears that it is not provided so after a search I found a template for a custom design using the ML501 SRAM and other peripherals the source of the UCF file is included as a comment in the constraint file heading section.

In addition it includes an SRAM model and SRAM controller for the 9Mb SRAM on board a similar ML506 board.


Look at the timing diagrams and state machine diagram in the datasheet to get a better idea of how to work with the SRAM module.

Hope this might help you and anyone else working with the ISSI SRAM.


Good luck.

The attached SRAM controller is in VHDL, which I later translated to Verilog.
The attached SRAM model is in Verilog.