mutiple constant driver

I have a hdl file to multiplex two input (8 bit width) to one output (8 bit width) select by sel1 and sel2 (both of them are differential input) . sel1 is rasing edge and sel2 is falling while sel1 falling edge and sel2 is rasing edge. The following file is written but after compilation Quartus said it is multiple constant driver .
Can someone help me ?

module mux3(sel1,sel2,data1,data2,data3);
input sel1,sel2;
input [7:0] data1;
input [7:0] data2;
output [7:0] data3;
reg [7:0] data3;
always @(posedge sel1)
begin
data3[7:0] <= data1[7:0];

end

always @(posedge sel2)
begin
data3[7:0] <= data2[7:0];

end
endmodule

lgeorge123 said:

sel1 is rasing edge and sel2 is falling while sel1 falling edge and sel2 is rasing edge

Click to expand...

I don't understand what you mean by that but the problem is that you are driving data3[7:0] from 2 different processes in a rising and falling edge and that is not possible.

Alex

the closest I can come up with:

As mentioned, the sel1/sel2 are just like inter-related clock signals and must meet setup/hold times relative to each other. Likewise, the output of this module is driven by combinatorial logic, which is less ideal. the output must meet the setup and hold times of the next register it drives. most likely, you will want to rewrite this code to use a single clock, and make sel1, sel2, and other signals be synchronous to that clock.

sel1 is rasing edge and sel2 is falling while sel1 falling edge and sel2 is rasing edge.

Click to expand...

Apparently, something gots confused here. Permute has worked out his own version of the logic, I'm not sure, if it's meeting the problem. You should better clarify what's actually intended.

If you possibly want to latch one input on the rising clock edge and the other on the falling edge of a clock, than you could use a DDIO register. It's a low level primitive (respectively a Quartus MegaFunction) that can't be inferred from HDL code but must be instantiated explicitely.

FvM said:

If you possibly want to latch one input on the rising clock edge and the other on the falling edge of a clock, than you could use a DDIO register

Click to expand...

I think permute code does that if i read it correctly, I'm using this way in vhdl, i have read it in an article but i can't find it now (found it https://www.edaboard.com/threads/195444/#post818994).

In a few words you use three signals
clk_out, set_clk_out, reset_clk_out

in one process you do set_clk_out <= not reset_clk_out; to set the clk_out to 1
in the second process you do reset_clk_out <= set_clk_out; to set the clk_out to 0

also you have to add in the architecture (out of the processes)
clk_out <= set_clk_out xor reset_clk_out;

then clk_out can be used anywhere

the two processes can have different clocks or falling and rising edge.

Alex

thanks all of your reply , sel1 and sel2 is a pair of differential output from AD9481 which is a fast AD converter . Can Permute ' code can be used in differential input of Altera EP2C8Q208C8 ? I have another problem , in order to test a program of which use EP2C8Q208C8 to drive a TFT LCD (7 " 800x480 18bit color TFT LCD) , a pcb of EP2C8Q208C8 with only SRAM(plus JTAG and AS) may be purchased (for testing purpose ), a sine wave with certain color with black background is displayed on this LCD and use a Quadrature Rotoary Encoder to move the sine wave upward and downward. Under this configuration can I use EP2C8Q208C8 without SDRAM ? Also If I compile the HDL file and SOPC of Quartus 9.1 will it show insufficient RAM message under no SDRAM condition in a large code ??

sel1 and sel2 is a pair of differential output from AD9481 which is a fast AD converter

Click to expand...

So Sel1 and Sel2 is actually DCO+/DCO- of the ADC. In this case, you should assign a differential I/O standard for the DCO input instead of combining them by logic, which isn't better than using one DCO line single ended.

Cyclone II can process DCO actually as a single ended (3.3V LVCMOS) signal, you don't necessarily need to feed it differentially. Differential signaling has the advantage of better interference suppresion and also reduction of generated common mode inteferences. To connect the 3.3V DCO output directly, the LVPECL IO standard fits best.

The best demultiplexing technique depend on what's the target for the combined data. It will be a 250 MHz clock domain, most likely clocked by the same clock source that drives the AD9481. So the data must be registered by the 250 MHz clock, not by 125 the MHz DCO clock. There are different options to process DCO, but they depend on your design's overall clocking scheme, mostly how the 250 MHz domain is related to DCO.

Regarding your TFT video generator question, EP2C8 hasn't sufficient internal RAM to buffer a video frame, so the only option is to generate the test data on the fly. This should be basically possible for a simple test pattern. To buffer the complete frame, external memory would be needed.

For assign differential input pin to Altera fpga , in Quartus -> assignment -> pin planner select lvds input is necessary , so I ask do above procedure and apply permute's code is it simply enough to multiplex two 8 bits data bus to one 8 bits data output with DCO+/DCO- ????

If its a differential input, you should just be able to use a differential buffer to get a single signal "sel", which is used the same as a normal mux.

is it simply enough to multiplex two 8 bits data bus to one 8 bits data output with DCO+/DCO- ????

Click to expand...

I would use a simple asynchronous select as a multiplexer. But the question is, if the 250 MHz data should be registered to the 250 MHZ clock domain.

according to FvM suggestion , a multiplexer can be used , I have no idea about differential signal , a raising edge and falling edge of differential signal can we viewed as logic high and low looking in multiplexer ???

Two input how can be solved , but how about four input clocks ????

Two input how can be solved , but how about four input clocks ????

Click to expand...

Are you referring to a particular application problem?

The following is my code which give a multiple constant driver:

module MUX1
(
CLK1,
CLK2,
CLK3,
CLK4,
CH1,
CH2,
CH3,
CH4,
CH_OUT
);

input CLK1;

input CLK2;

input CLK3;

input CLK4;

input [7:0]CH1;

input [7:0]CH2;

input [7:0]CH3;

input [7:0]CH4;

output reg [7:0]CH_OUT;

always @(posedge CLK1 )
begin
CH_OUT <= CH1;
end

always @(posedge CLK2 )
begin
CH_OUT <= CH2;
end

always @(posedge CLK3 )
begin
CH_OUT <= CH3;
end

always @(posedge CLK4 )
begin
CH_OUT <= CH4;
end

endmodule

my code which give a multiple constant driver

Click to expand...

That's for sure. At the end, you'll need a chain of multiplexers to combine the four inputs to one output. To achieve this without timing violations, the relation of the "clock" and data signals, and their actual speed should be known.

The problem is about designing a hardware circuit that can combine the signals.