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EDIF netlist access in Xilinx ISE 8.1i

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jahanzebanwer

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I am using Xilinx Project Navigator ISE 8.1i. I want to access the EDIF netlist of my program which is write as a behavioral verilog code. Suppose I write the code (a+b), than I could see in the RTL and Technology schematics that a full-adder has been created inside a LUT but i want to access the EDIF netlist of this RTL diagram created by XIlinx.
Moreover, I learned in the Xilinx Development Reference Guide that the NGD netlist is a logical description of the circuit whereas the NGD netlist Xilinx created for my programs are totally vague. It seems like it is based on the local primitives of the xilinx board but atleast no logical description is available.
Thanks for your time.
 

synthesize your design with xst and then use ngc2edif.exe from command line to translate the *.ngc netlist to EDIF format.

ngc2edif.exe path is C:\Xilinx\11.1\ISE\bin\nt , in version 8 it is probably C:\Xilinx\8.1\ISE\bin\nt or do a search in the installation folder

Alex
 

alexan_e said:
synthesize your design with xst and then use ngc2edif.exe from command line to translate the *.ngc netlist to EDIF format.

ngc2edif.exe path is C:\Xilinx\11.1\ISE\bin\nt , in version 8 it is probably C:\Xilinx\8.1\ISE\bin\nt or do a search in the installation folder

Alex
Click to expand...

Dear Alex
I have been able to go to this path and can find ngctoedif as an application (in windows vista). But when i run it, it opens as a command line and instantly disappears. So, by command line, do you mean to run this application only ?
Thanks for your time.
 

Do a search for the file using windows and you will find it.
The application has some parameters it needs

Release 11.4 - ngc2edif L.68 (nt)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.

Usage: ngc2edif [-bd angle|paren|square|asis] [-intstyle ise|xflow|silent] [-log <log_file>] [-w] <infile> [<outfile>]

-bd <bus_format> Specify the bus delimiter to be used in the output edif.
The argument bus_format is required and could be of type
angle (bus notation would be bus<msb:lsb>
paren (bus notation would be bus(msb:lsb)
square (bus notation would be bus[msb:lsb]
asis (the bus delimiters in the input NGC will be preserved
If -bd is not used, one of bus delimeter types in the input
NGC file would be used in the output EDIF netlist.

-log log_file Specify log file (Default is ngc2edif.log).

-intstyle silent Reduce screen output with silent style mode.

-w Overwrite the output file

<infile> Input File: '.ngc'.

<outnetlist> Output netlist file name. Default is '<ngcfile>.ndf'

<outncf> Output Constraint file name. Default is '<outnetlist>.xncf'

ngc2edif translates an NGC file into an EDIF netlist which is intended for use
within supported synthesis tools as a means of determining resource / timing
estimates. The EDIF is defined in terms of Xilinx Library Primitives (Unisims).

i haven;t used it but you need to write something like
C:\Xilinx\11.1\ISE\bin\nt\ngc2edif.exe C:\Projects\test\xilinx_dso.ngc C:\Projects\test\xilinx_dso.edif
I also don't know about the bus format

Alex
 
Thank you so much Alex. I am now able to convert to EDIF files as required. Thanks a lot.

Jahanzeb
 

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