otis
Member level 3
Reading verilog port with in the same module- What is the problem?
Hi,
I know in VHDL we cannot read the port within the module.
it is possible in Verilog. I used in few places. My colleague says it is wrong. But he does not know why.
I also dont know why.
Could anyone tell what is the problem using/reading output port with the same module in Verilog?
Thanks in advacne
Hi,
I know in VHDL we cannot read the port within the module.
it is possible in Verilog. I used in few places. My colleague says it is wrong. But he does not know why.
I also dont know why.
Could anyone tell what is the problem using/reading output port with the same module in Verilog?
Thanks in advacne
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