Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

CTS transition target

Status
Not open for further replies.

cffyh

Newbie level 5
Joined
Sep 29, 2010
Messages
10
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,336
The highest clock frequency of design is 2M.
Does 2ns trsnsition target tough for CTS?
This is my first time to do CTS.
 

Hi, the best way to estimate the delay and the skew or uncertainty is to count up (or estimate) the number of flops on a particular clock. Using this count, ask your silicon vendor (or your CTS expert) what is a typical insertion delay and skew for this number of flops in the target technology. The technology and depth of the tree, not necessarily the clock frequency, determine insertion delay and skew.
 
  • Like
Reactions: hawker

    hawker

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top