Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi, the best way to estimate the delay and the skew or uncertainty is to count up (or estimate) the number of flops on a particular clock. Using this count, ask your silicon vendor (or your CTS expert) what is a typical insertion delay and skew for this number of flops in the target technology. The technology and depth of the tree, not necessarily the clock frequency, determine insertion delay and skew.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.