Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Start statemachine without clock

Status
Not open for further replies.
O

otis

Member level 3
Joined
Sep 21, 2010
Messages
60
Helped
4
Reputation
8
Reaction score
3
Trophy points
1,288
Activity points
1,711
Hi,
I have a state machine. In a particular state the system goes to power save mode where the clock will be stopped.

At this state the state machine looking for an external signal, when It gets the statemachine sends a signal to analog block to start the clock and when it get the clock it will continue the state machine.

The state machine is synchronous but in power save mode it should wakeup for asynchronous signal. How do make the SM to react on this signal without clock.

How this particular state can be done?

the design will be done in Verilog

Any input are highly appreciated.
 

Why don't you just use the async signal, may be after synchronization if necessary, to gate the clock ?
 
  • Like
Reactions: otis

    O

    otis

    Points: 2
    Helpful Answer Positive Rating
I made similar work few years ago.
Here is an example.

// pwrsave register - send signal to analog block
// 0 - CLK ON
// 1 - CLK OFF

wire resp = res & !flag;
wire reset_flag = res & self_res;

always @(posedge clk or negedge resp)
if(~resp)
pwrsave<=1'h0;
else if(write_ena)
pwrsave<=T[15];// write data to bit

//interrupt sets FLAG -> resets PWRSAVE
always@(posedge interrupt or negedge reset_flag)
if(~reset_flag)
flag<=1'b0;
else
flag<=1'b1;

always@(posedge clk or negedge res)
if(~res)
flag_delay<=1'h0;
else
flag_delay<=flag;

always@(negedge clk or negedge res)
if(~res)
self_res<=1'b1;
else if(flag_delay)
self_res<=1'b0
else
self_res<=1'b1;
 
  • Like
Reactions: otis

    O

    otis

    Points: 2
    Helpful Answer Positive Rating
Thanks for your replies.

to kornukhin
for me the code is little confusing. Where the state machine starts without clock?

thanks in advance for your reply
 

"The state machine is synchronous but in power save mode it should wakeup for asynchronous signal. How do make the SM to react on this signal without clock."
"Where the state machine starts without clock?"

State machine starts on positive edge of async signal (clock can be off or on).

positive edge of interrupt (async signal) -> flag=1 -> pwrsave=0 -> CLOCK ON
 
  • Like
Reactions: otis

    O

    otis

    Points: 2
    Helpful Answer Positive Rating
Thanks for your reply!
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top