Global vdd and gnd (vdd! and gnd!) in Cadence

Hi All

I have a difficulty to use global power and ground in Cadence. I am using Spectre.
By using "!" with vdd or gnd, you make them as global. They are recognized in different hierarchy in schematic simulation, so no problem. However, they are not recognized in layout (extracted) simulation.
As you know, there are two common ways to use global nodes. One way is using vdd and gnd symbols and directly connects to a block of your circuits. Another way is giving pins and name them vdd! and gnd!. In either way, there will be no physical nodes to connect to a power source and ground. Simulation in Spectre is no problem in another cellview as a testbench after replacing the symbol.

However, the simulation won't work in layout because the global nodes are not recognized in different hierarchy. For example, let's say an inverter with gnd! and vdd! instead of vdd and gnd. Then there will be no more physical nodes for vdd! and gnd! in symbol view. After placing the symbol in a different cellvew as testbench for simulation, the result does not come out right. For easy test to check whether vdd! works or not, the input pulse signal into the inverter is set at 2.5v. Then, the voltage of vdd is changed to 4v. However, the inverter output is still 2.5v. As matter of fact, it does not invert the input signals. As soon as I change the simulation from the extracted to schematic, the signals are inverted at different voltage level which is 4v.

I believed that it would be the global bonding problem. Therefore, I used "Config" cellview from "Hierarchy Editor". It gave me the same wrong result.
Some recommends using Verilog, but it requires some initial setup which I can't access.
Some recommends using ".CONNECT", but not available in our Cadence
I have found some posts in this forum regarding to the same issues, but there is no such a good answer so far.
Anybody gives me a good solution
Thank you

vdd! and gnd! as named-net globals work the same as they have
for decades, in schematic based design.

If you want the nets to be picked up in the extracted view, and
called gnd!, then you will have to place a gnd! pin polygon at
the top level on the appropriate bus.

You can force pin-tagged nets without physical connection
to be merged. I believe I've seen options that let you do this
at top, or down levels of hierarchy.

But when in doubt, hook it up realistically.

You can put schematic pins with vdd! and gnd! that will produce
a symbol with those pins, but that defeats the purpose of
not having to add wires to the wireball.

There is no such thing as a global layout node, with the possible
exception of sub! (which is only a single node, if you are not
very demanding of electrical accuracy).

Thank you dick_freebird

Having your words in mind, I made it work

The easiest way for this is simply adding pins for vdd! and gnd! in symbols

Thank you

dick_freebird said:

vdd! and gnd! as named-net globals work the same as they have
for decades, in schematic based design.

If you want the nets to be picked up in the extracted view, and
called gnd!, then you will have to place a gnd! pin polygon at
the top level on the appropriate bus.

You can force pin-tagged nets without physical connection
to be merged. I believe I've seen options that let you do this
at top, or down levels of hierarchy.

But when in doubt, hook it up realistically.

You can put schematic pins with vdd! and gnd! that will produce
a symbol with those pins, but that defeats the purpose of
not having to add wires to the wireball.

There is no such thing as a global layout node, with the possible
exception of sub! (which is only a single node, if you are not
very demanding of electrical accuracy).

Click to expand...

Hello

I just came across ur old post regarding vdd! and gnd!, and was wondering if could you please help me wid the same?

I have named my layout vdd!and vss! and in schematic power rails as vdd!(vdd_inherit) and vss!(vss_inherit) .

But wen i want to do a test bench simulation,these i dono how do i link vdd! to vdd and vss! to gnd .The ouput is not as expected for eg. for a inverter.


And as u suggested to use pins in symbol, i tried that method but it doesn seem to work for me.

It woudl be great if you could help me out with it !

Thanks in advance

BB