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Parameterized module in Verilog

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talent_engin

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Hi all,
I am running an exitsing verilog code using Synopsys Design Compiler (version 2006 or 2009 or 2010). The code containing several parameterized modules that caused the following warnings when I link the design:

Warning: Cannot find the design 'secret_number' in the library 'WORK'. (LBR-1)
Warning: Unable to resolve reference 'secret_number' in 'testing'. (LINK-5)

The original code is sth like this:

//This is the reference module

module secret_number
#(parameter WIDTH = 5)
(input [WIDTH-1:0] WE,
output [WIDTH-1:0] QE);
endmodule


//this module calls a secret_number module:
module testing (IN, OUT);
input IN;
output OUT;
secret_number #(5) S1
(
.WE (),
.QE ()
);
endmodule



I have checked the syntax used to initiate a parameterized module in Verilog. There are a few ways:
1. Using defparam
2. Using the #(Parameter_valule_list) form
3. Using the #(.Parameter(value)) form.

None of these works for me. The thing is if I call the module without passing a new parameter value (i.e. in the above code, I remove #(5)), the code works perfectly normal.

When I pass a new value to the module, It cannot be resolved.
Any one knows what's going on here? and how to solve this.
Thanks a million.
 

Hi,

As far as I see, your code is correct. However your secret_number module uses Verilog-2001 ANSI style for the ports. Maybe Synopsys Design Compiler does not support this.

You could rewrite it to:
Code:
module secret_number(WE, QE);
parameter WIDTH = 5;
input [WIDTH-1:0] WE;
output [WIDTH-1:0] QE;
endmodule

Maybe this solves your issue.

Devas
 
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