mbenton
Newbie level 6
Hello,
Using Xilinx's Architecture Wizard I generated a DCM block. I added the generated vhdl(test.vhdl) file to the project and copied the ucf generated file in my ucf file. I am getting this error
I have read in an older thread on xilinx.com that I have to write the full hierachical path instead of just DCM_INST. Maybe my question is stupid but I dont know how I can find the full hierachical path of the instance names in my design. Could anyone give me a pointer in doing this?
Thank you,
Michael
Using Xilinx's Architecture Wizard I generated a DCM block. I added the generated vhdl(test.vhdl) file to the project and copied the ucf generated file in my ucf file. I am getting this error
I tried changing the ucf part from DCM_INST to "test/DCM_INST" but the error persits.NgdBuild:981 - Could not find any associations for the following constraint:
'<INST DCM_INST CLK_FEEDBACK = 1X;> [temp_bld0.ucf(143)]'
I have read in an older thread on xilinx.com that I have to write the full hierachical path instead of just DCM_INST. Maybe my question is stupid but I dont know how I can find the full hierachical path of the instance names in my design. Could anyone give me a pointer in doing this?
Thank you,
Michael