How to resolve this error (it's related to Conformal)

When I ran the Conformal, I encounted non-equivalent..
So, I analyzed non-equivalent point using the command "analyze_nonequivalent 12542"

its output is as below,

//------------------------------------------------------------------------------
Analyzing non-equivalent compared points:
(G) + 12542 DFF /I_AR_TOP/I_ce_stop/I_ARFFT/I_fftv2_run_even_top_multi_core_viarom_rtl/run_even_top_viarom_multi_core_inst[1].u_fftv2_run_even_top_viarom_rtl/r22sdf_compuation_block[4].gen_r22sdf_compuation_block.u_fftv2_basic_run_rtl/FIFO_bRAM_eRAM_stg1.u_bf1_fftv2_fifo_rtl/u_fifo_sc/mem_do_n2x_reg_reg[23]
(R) + 7855 DFF /I_AR_TOP/I_ce_stop/I_ARFFT/I_fftv2_run_even_top_multi_core_viarom_rtl/run_even_top_viarom_multi_core_inst[1].u_fftv2_run_even_top_viarom_rtl/r22sdf_compuation_block[4].gen_r22sdf_compuation_block.u_fftv2_basic_run_rtl/FIFO_bRAM_eRAM_stg1.u_bf1_fftv2_fifo_rtl/u_fifo_sc/mem_do_n2x_reg_reg[23]/Q_reg
Compared points' clock are non-equivalent.
Following module is black-boxed in one design, while not in the other:
(G) eclkgen_act_DIVQ115_DIVQ27_DIVQ33_DIVQ43_DIVQ515_DIVQ6127_DIVF0_DIVR0_RANGE4_POL0_BYP682_FBS1_SYNCRESET1_VSEL3 /I_ClkGenPLL/clkwizard_ins/eclkgen_inst
Following module is black-boxed in one design, while not in the other:
(R) eclkgen_act /I_ClkGenPLL/clkwizard_ins/eclkgen_inst
Compared points' data are non-equivalent.
Following module is black-boxed in one design, while not in the other:
(G) regfile_w32r32an$i_regfile$OF$rf_w32r32an$layer2$OF$_rfile_an$layer1$OF$eip_n2x_rfile_inst_WIDTHR32_WIDTHW32_MODERx00004153594e43_STALL20047_INIT_ON20047_INIT_MASTER_FILE0_INIT_MASTER_WIDTH0_INIT_MASTER_DEPTH0_INIT_TYPE4736344_INIT_ROM20047_INIT_STARTW0_INIT_STARTB0_COMP_INITFILE_PREFIXx636f6d706f6e656e7446696c65 /I_AR_TOP/I_ce_stop/I_ARFFT/I_fftv2_run_even_top_multi_core_viarom_rtl/run_even_top_viarom_multi_core_inst[1].u_fftv2_run_even_top_viarom_rtl/r22sdf_compuation_block[4].gen_r22sdf_compuation_block.u_fftv2_basic_run_rtl/FIFO_bRAM_eRAM_stg1.u_bf1_fftv2_fifo_rtl/u_fifo_sc/mem0/single_row_blk.row/column_block[0].inst/read_mode.layer1/w32_block.inst_w32r32an_block.layer2/i_regfile
Following module is black-boxed in one design, while not in the other:
(R) regfile_w32r32an /I_AR_TOP/I_ce_stop/I_ARFFT/I_fftv2_run_even_top_multi_core_viarom_rtl/run_even_top_viarom_multi_core_inst[1].u_fftv2_run_even_top_viarom_rtl/r22sdf_compuation_block[4].gen_r22sdf_compuation_block.u_fftv2_basic_run_rtl/FIFO_bRAM_eRAM_stg1.u_bf1_fftv2_fifo_rtl/u_fifo_sc/mem0/single_row_blk.row/column_block[0].inst/read_mode.layer1/w32_block.inst_w32r32an_block.layer2/i_regfile
Analysis of non-equivalent compared points:
Unbalanced black box. (Occurrence: 4)
//-------------------------------------------------------------------------------------


In first case, "Compared points' clock are non-equivalent" <-- How I slove this problems?, I checked the clock pin of both of golden and revised. but its clock pin seems correct connection.

plz, give me advices,
Thanks,

Bymin

Hi,bymin5
perhaps, the BBOX "eclkgen_inst" in Golden and Revised wasn't mapped for extra name "DIVQ115_DIVQ27_DIVQ33_DIVQ43_DIVQ515_DIVQ6127_DIVF0_DIVR0_RANGE4_POL0_BYP682_FBS1_SYNCRESET1_VSEL3 " in golden, you may map the two "eclkgen_inst" first, and run lec again.
hope it helps!

Thanks for your reply.

btw, Should I use the command "add_mapped_points ID ID"
that is

add_mapped_points 12542 7855

is it right?

yes, just the command "add mapped points ID ID", can it help?

Hi Vonkloud,

Thanks a lot,
I solved by doing this in LEC mode.
but I don't know why this problem was happened.
Does it map the blackbox automatically?

and btw, I used the command "write_hire_compare_dofile" in lec-script file.
it that case, how can I add the command "add_mapped_points ID ID" ?

Hi,bymin5
1, The conformal does map the blackbox automatically, while it map each other by name first. In your case, i think golden design is the netlist after synthesis, cause some parameters appeared in instance eclkgen_act's name, it was brought on instantiation during synthesis. if u manully change the instance name "eclkgen_act_DIVQ115_DIVQ27_DIVQ33_DIVQ43_DIVQ515_DIVQ6127_DIVF0_DIVR0_RANGE4_POL0_BYP682_FBS1_SYNCRESET1_VSEL3 " to "eclkgen_act" in golden design(netlist or rtl? i'm not sure), the lec will also pass.

2,You often don't know which module or instance will not be mapped before u run the first lec, the command "write hire_compare dofile" is just generate a general hier.do, u can maully insert the command "add mapped points ID ID" behind "set system mode lec" in the submodule lec's scripts in hier.do, and then run hier dofile again. u should confirm the two submodules are mapped while the tools can not map them automatic for some reasons!

Hi Vonkloud,
Thanks a lot, your advice was helpful.

How about adding the below option to the command "write_hier_compare_dofile" ?

--> -extract_clock

the reason why I try to add this option is that the message "Compared points' clock are non-equivalent" in the log was caused by "unbalanced - black box"


//---------------------------------------------------------------------------------------

set write_opt

• 
  set write_opt [concat $write_opt -extract_clock]
  set write_opt [concat $write_opt -constraint]
  set write_opt [concat $write_opt -usage]
  set write_opt [concat $write_opt -conditional]
  set write_opt [concat $write_opt -INPUT_OUTPUT_Pin_equivalence]
  set write_opt [concat $write_opt -Threshold 500]
  
  write_hier_compare_dofile ./hier_ASIC_TOP.do -replace $write_opt
  //-------------------------------------------------------------------------------------
  
  Added after 2 minutes:
  
  by the way,
  " eclkgen_act_DIVQ115_DIVQ27_DIVQ33_DIVQ43_DIVQ515_DIVQ6127_DIVF0_DIVR0_RANGE4_POL0_BYP682_FBS1_SYNCRESET1_VSEL3 "
  
  the above module is golden (RTL)
  
  Thanks,
  Byungyoon Min

Hi bymin5,
Frankly speaking, I didn't use the option "-extract_clock" before,
i just read the command reference about this option in "write_hier_compare_dofile", it seems will be work
when clock ports are not mapped between two design for
the different names.
In your case, "Compared points' clock are non-equivalent" is the result, not the reason which cause the issue. In my opinion, if two modules or BBOXs are non-equivalent caused by its clock pin wasn't mapped , the option "-extract_clock" perhaps will be help.

Anyway, you can have a try.

Thanks a lot,

Anyway, I solved it by using the command "add_mapped_points" as you recommended. I appreciate it again.

Now, I try to do it as it was mentioned...