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Help me on 10 bit ADC model in Simulink

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timbu007

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ADC

Dear All,
I am trying to implement a 10 bit ADC model in Simulink.
When the input voltage of 5V(sine wave) is provided the outputs obtained on the scope are all 1's(1111111111).When the input is changed to some other value such as 3V the output bits are something different than expected.
As per calculations:
Step size=5V/1023=0.00489.
if for 5 binary has to be 1111111111(1023)
For 3 binary 1001100101(613)
The binary output for 3 I am getting it as 1100110011 which equals to decimal equivalent of 819.
I also provided a dc of 3 I got the same output as the above
Please correct me what is going wrong in the method
Really need your help.
Thanks in advance.
 

ADC

Your calculations are correct, your simulink model is not.
 

    T

    timbu007

    Points: 2
    Helpful Answer Positive Rating
Re: ADC

JoannesPaulus said:
Your calculations are correct, your simulink model is not.
Click to expand...

Thanks for your reply.i will look into it and keep posted on this forum.
 

Re: ADC

JoannesPaulus said:
Your calculations are correct, your simulink model is not.
Click to expand...

Attached is the schematic of the pipeline stage and the error correction which I am using. As per my understanding the last bit will not have error correction. Please correct me if i am wrong.
What is the error correction in pipelined adc?I would be very much thankful if the concept can be explained.I think there is some problem with my error correction logic.
Thanks once again.
 

I believe your gain 2 block should be after the addition, just before the output.
 

JoannesPaulus said:
I believe your gain 2 block should be after the addition, just before the output.
Click to expand...
Thanks again.But I did try that also but it did not work out.How is the output expected for a 10 bit?I mean after error correction when checking the bits do we have to use any 2's complement or any step or the final output on the scope would be the answer as required(i.e the number of bits)
 

I do not really understand what your correction_error block does since I do not know what are the inputs and how the output is used but the gain block should definitely be after the adder (in all the pipeline stages).

Moreover, are you accounting for the pipeline delay in your final adder?
 

JoannesPaulus said:
I do not really understand what your correction_error block does since I do not know what are the inputs and how the output is used but the gain block should definitely be after the adder (in all the pipeline stages).

Moreover, are you accounting for the pipeline delay in your final adder?
Click to expand...

Thanks.The inputs to the error correction block come from the delay blocks which have their inputs from the comparator 1 and the XOR output in the input stage.
Attached is the entire block for the same.Thanks once again for all your help.[/img]
 

As I suspected, you are not accounting for the pipeline delay correctly. You need to align the samples of each stage, i.e. the first stage needs to be delayed 9 clock cycles, the second stage needs to be delayed 8 clock cycles, ... , the ninth stage goes into the adder.
In your case you are adding the quantization of different steps.
 

JoannesPaulus said:
As I suspected, you are not accounting for the pipeline delay correctly. You need to align the samples of each stage, i.e. the first stage needs to be delayed 9 clock cycles, the second stage needs to be delayed 8 clock cycles, ... , the ninth stage goes into the adder.
In your case you are adding the quantization of different steps.
Click to expand...

Thanks JoannesPaulus for your feedback.You mean to say that along with providing delay blocks for ADC bits,I also need to provide delays to the output of the DAC i.e in common terms the residue voltage of the 1st stage(after the sum block) which acts as an input voltage for the 2nd stage should also be provided with delay clock in terms of 9,8,7 upto 1 delay cycles...right?Please correct me if I understood it wrong.
Anyways thanks a lot again for your help.
 

timbu007 said:
You mean to say that along with providing delay blocks for ADC bits,I also need to provide delays to the output of the DAC i.e in common terms the residue voltage of the 1st stage(after the sum block) which acts as an input voltage for the 2nd stage should also be provided with delay clock in terms of 9,8,7 upto 1 delay cycles...right?Please correct me if I understood it wrong.
Click to expand...
No, the decreasing delays should just be on the digital path.
 

    T

    timbu007

    Points: 2
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JoannesPaulus said:
timbu007 said:
You mean to say that along with providing delay blocks for ADC bits,I also need to provide delays to the output of the DAC i.e in common terms the residue voltage of the 1st stage(after the sum block) which acts as an input voltage for the 2nd stage should also be provided with delay clock in terms of 9,8,7 upto 1 delay cycles...right?Please correct me if I understood it wrong.
Click to expand...
No, the decreasing delays should just be on the digital path.
Click to expand...

I have inserted delay blocks in the input stage for the digital outputs in the model.The delay blocks are having 9 D-flip flops in the 1st stage in decreasing order to the last stage having 1 flip flop.
Is the XOR block required or directly the D1 and D0 from the comparators can be taken?
Thanks
 

timbu007 said:
Is the XOR block required or directly the D1 and D0 from the comparators can be taken?
Click to expand...
I would send out just the output of the adder -1 (the output should be between 0 and 2), then add all the properly delayed outputs with a simple adder. No XOR needed.
 

    T

    timbu007

    Points: 2
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JoannesPaulus said:
timbu007 said:
Is the XOR block required or directly the D1 and D0 from the comparators can be taken?
Click to expand...
I would send out just the output of the adder -1 (the output should be between 0 and 2), then add all the properly delayed outputs with a simple adder. No XOR needed.
Click to expand...

Thanks a lot once again.I did indeed put delay blocks in descending order from 9 to 1 flip flops at the digital output.But I am still not able to get the required output.

I feel the my comparator block in the Sub ADC seems to be giving the problem.
In the Sub ADC block I have made the comparator blocks as follows:
for 0.5 Maximum input(According to the concept of +Vref/4 and -Vref/4)
D1 Vin>=0.125
D0 Vin>=-0.125
so Vin will be compared to values like 0.4,0.3,-0.1 etc.
Pass these values as ADC digital output through delay blocks and to error correction and also to the Sub DAC block to pass on to the next stage.
All help your help is really appreciated.
Thanks a ton for your time and patience.
 

JoannesPaulus said:
timbu007 said:
Is the XOR block required or directly the D1 and D0 from the comparators can be taken?
Click to expand...
I would send out just the output of the adder -1 (the output should be between 0 and 2), then add all the properly delayed outputs with a simple adder. No XOR needed.
Click to expand...

I would really be glad if you could please help me out in this pipeline ADC in fixing the possible error.Its like a block and I am not able to fix it.Thanks a ton in advance.
If you could just show me the error in the block in the model I think I will be able to comprehend it better.
Thanks a lot for your patience in answering my queries.
 

After spending some time on your design, I realized it was based on this one (provided by someone in this forum some time ago). Please, check your design against it.
 

    T

    timbu007

    Points: 2
    Helpful Answer Positive Rating
JoannesPaulus said:
After spending some time on your design, I realized it was based on this one (provided by someone in this forum some time ago). Please, check your design against it.
Click to expand...

Thanks a lot for your help.But I think the same problem arises

Resolution would be 5V/1023=0.00489.For 5V it would be 1111111111
For 5-0.00489=4.99511.The value would be 1022.
For 4.99511-0.00489=4.99022 the value is the same 1022 which I think should be 1021.
Please correct me.Please find attached the screen shot taken for the scope.I am checking the values(for Vin=4.99022) which fall on the white line.Let me know if I am seeing it right.

Thanks in advance.
 

JoannesPaulus said:
I believe the full-scale is 10, not 5.
Click to expand...

Hi All,
I am new to this forum.As this topic was already in progress I did not want to start a new thread.I have already built a pipeline adc.I get the 10 bit output on the simulink scope.
I was wondering while performing FFT testing for ADC how will this data(bit output) be fed to the FFT scope in simulink. What would the test setup for ADC be in simulink.
All help would really be appreciated?
Alan
 

Hello guys!

Does anyone know how to create the block in simulink to convert to binary code from the value i.e. 12v 4-bits, 12v 9-bits.
Thank you
Kyle

Added after 3 minutes:

I have to build the sys model for digital current control with bits and max voltage. for i have to know the output in binary code for my DPWM.
 

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