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Help me use power analysis in DC

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vivek_p

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I want to analyze the power of a design using Synopsys Design Compiler(DC).

1) First I set the Synopsys libraries
2) Read verilog files
3) Compiled the design
4) Checked the power (using "report_power" command)
5) Created the clock and set constraints
6) Once again compiled the design
7) Checked the power (using "report_power" command)

In the 4th step I got the power of the entire design to be 1.1 mW
In the 7th step I got the power of the entire design as .5 mW

The 7th step gives the clock power, then what does power in step 4 refer to?

Can anyone help me to find the power of the design using DC......

And one more thing I can only find the Dynamic power of the design , how can I get the leakage power
 

Power Analysis in DC

Hi,

The power analysis being done at step 7 is correct as it involves the actual design with clocks and constraints applied. DC will do the optimization of the design and then calculate the power.

Power in step 4 refers to the design without constraints (and thus inefficient optimization)

For the second question of leakage power, I also don't know the complete answer, but I guess the correct calculation of leakage power can be done after P & R only.
 

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    vivek_p

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Re: Power Analysis in DC

Can anyone please comment more on power analysis in DC
 

Re: Power Analysis in DC

I have heard that we have to add powers obtained in step 4 and step 7. Is there any significance in this????
 

Power Analysis in DC

Hi,
for the first one, both the power values are correct. The latter one is more acurate while the first one was coming form default synthesis.

for the second one, I just do it using Prime Power. for averager power, we read asif file. And for other power, we read vcd files. So I guess you could using vcd file to get other power.
 

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    vivek_p

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Re: Power Analysis in DC

Can you plesae explain the various steps involved in using Prime Power.............................I am a Synopsys newbie
 

Re: Power Analysis in DC

vivek_p said:
Can you plesae explain the various steps involved in using Prime Power.............................I am a Synopsys newbie
Click to expand...

Hi, this is my step:
1,set link_library
set search_path
2, read_verilog (gate_level)
3, read_vcd (dependent on your testbench, extract toggle information)
4, read_parasitic
5, set constraints and other working environment
6, set_wavform_option
7, calculate_power
8,report_power and power waveform.

i think that's all
 

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    vivek_p

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Power Analysis in DC

synopsys now use PTPX report power. please refer to STA doc.
 

    V

    vivek_p

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Re: Power Analysis in DC

Can anyone please explain more on power analysis
 

Power Analysis in DC

To get leakage power, the .lib you use must have the leakage power information in it. DC will sum the leakage power numbers of all the cells used in the design to produce the final leakage power number. As for dynamic, in Step 4, since you have not defined any clocks, the tool will assume a default toggle rate and default toggling probability (check description of following variables in DC man: power_default_toggle_rate and power_default_static_probability). These values are applied to ALL nodes in the design and hence may not be realistic. When you define clocks with specific frequencies, the results become more accurate. It is even more accurate if you load a VCD since all toggling information for each node in the design in present in it.
 

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    vivek_p

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Re: Power Analysis in DC

@ D Saurabh

Can you please explain more..........

Added after 9 minutes:

In a design I have gated the clock with an input using an AND gate

The clock will be gated when the input is "zero"

If I analyze the power wiill I gate the clock gated power or normal power.

How can the design know the value of the input ( whether it is '1' or '0')

Help needed..........urgent

Thanks in advance
 

Power Analysis in DC

Hi,
For this you need to load a VCD. The VCD will have the information of toggling activity at all nodes including clock gates and thus calculates the power more accurately.
Else, I suppose you can do a set_case_analysis on the clock gate input to make it '0' and then report power.
 

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    vivek_p

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Re: Power Analysis in DC

Can you please write a simple script for doing this in Synopsys DC
 

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