Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Which metal layers we use for Clock Tree Synthesize?.

Status
Not open for further replies.

kumar_eee

Advanced Member level 3
Joined
Sep 22, 2004
Messages
814
Helped
139
Reputation
276
Reaction score
113
Trophy points
1,323
Location
Bangalore,India
Activity points
4,677
CTS Route Metal

Which metal layers we use for Clock Tree Synthesize?.

Let say, the top most metal is 7.

Now, my question is which metal layers we use for CTS route?.
 

Re: CTS Route Metal

According to me for CTS higher metal layer is used. since clock goes to every where and it switches fast so resistance of metal should be as slow as possible and capacitance also, since higher metal layer are thicker and wider it is best suit for CTS.

Let others flash on this.

--
Shitansh Vaghela
 

Re: CTS Route Metal

Generally, the top-most layer is reserved for the power routing. The layer that is immediately below the top-most metal layer can be utilized for clock routing. I am not sure whether clock routing can share the top-most layer with power routing. Can somebody clarify this?
 

Re: CTS Route Metal

Yes, clock routing can share the top-most layer with power routing.

for e.g : out of 7 LM we can use 6&7 for power routing and 5,6&7 for clock routing instead of 4&5 for clock routing. So we can have more routing resources for signal routing.


Jit
 
Re: CTS Route Metal

in soc encounter it uses metal 3 and 4 by default in cts
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top