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SOC Encounter-Spacing violations

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ksrinivasan

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Hi friends

I am using soc encounter 8.1 for a digital ASIC design. When i complete my Nano route, i get some 400 spacing violations. Iam attaching the picture for ur refernce. Can someone tell me how I should correct the violations. I dont want to clear the violations, but to correct the violations

Thanks in advance
 

Click the bar under "All Colors" on the right to switch to physical view. Now check the following to see inside the macro
Cell Blockage
Instance Pin

Also make sure Routing Blkg is checked. Now you may be able to see why the spacing violations are comming up.

Not sure what is causing this without more info ... you can try to do verifyGeometry before you use nanoroute to be sure its nanoroute causing these ( and these are not some preroutes)
 
may I ask which technology are you using? I have same problems with NANGATE 45nm. They are before nano route, after preroute P&G rails. It seems there are some pins in the library too close to the power rail after preroute.
For me it seems it is library problem, not tool's problem.
Correct me if I am wrong.
 

Hi

i tried using verify geometry. It shows 56 violations
Regarding the spacing violations, i tried to change the orientation of the pads. It worked.
I could reduce the violations from 400 to 200.
But still strugling with 200 violations.
These r specifically with input and output pds and two inout pads
I have attached the two screenshots which are involved in the spacing violations

Thanks in advance
Sirnivasan
 

    D

    dreadQ

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In this case, the pin you are routing to is internal to the pad macro. It looks like this pin is surrounded by blockages.

Again, turn on "Instance Pin" and "Cell blockages" and start turning on/off each metal layer to get a pickture of what the routing/blockages look like inside the macro.

Just a thought .... You said this is an IO pad cell. What pin is this? Where is the other end connected to? It looks like its name is "pad" which makes me think this is the pad pin that gets connected to the outside of the chip. If so, there shouldn't be any routing on this. Check your verilog to see if this gets connected internally, or if this gets connected to your top level port list.
 

Hi

I went through it in detail
I feel there is some problem with the spacing of wire
I have sent the screenshot of the violation browser
Can u check out and help me out
 
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