Help solve bad default binding error in a VHDL code

Hi All,

I am new to digital design. I tried to simulation my VHDL code including the testbench (see below).

library IEEE;
use IEEE.std_logic_1164.all;

entity tb_keypad is

end tb_keypad;

architecture behaviour of tb_keypad is

signal keypad_in : std_logic_vector(6 downto 0);
-- signal dec_in : std_logic_vector(3 downto 0);
signal clk : std_logic :='0';
signal reset_N : std_logic;
signal count : std_logic_vector(2 downto 0);
-- signal count : std_logic;
signal dec_out : std_logic_vector(3 downto 0);
signal accept_out : std_logic;
signal error_out : std_logic;

component keypad
port (keypad_in : in std_logic_vector(6 downto 0);
-- dec_in : in std_logic_vector(3 downto 0);
clk : in std_logic;
reset_N : in std_logic;
count : inout std_logic_vector(2 downto 0);
dec_out : inout std_logic_vector(3 downto 0);
-- count : out std_logic;
accept_out : out std_logic ;
error_out : out std_logic);

end component;

begin

test_unit : keypad
port map (keypad_in => keypad_in,
clk => clk,
count => count,
dec_out => dec_out,
reset_N => reset_N,
accept_out => accept_out,
error_out => error_out);


test_block : block
begin
keypad_in <= "0001010",
"0000010" after 100 ns,
"0000100" after 200 ns,
"0000110" after 300 ns,
"0001000" after 400 ns,
"0001011" after 500 ns,

"1111010" after 600 ns,
"1110010" after 700 ns,
"1110100" after 800 ns,
"1110110" after 900 ns,
"1111001" after 1000 ns,
"1111011" after 1100 ns;

reset_N <= '0', '1' after 50 ns, '0' after 100 ns, '0' after 200 ns;
clk <= not clk after 30 ns;

end block;
end behaviour;


library IEEE;

use IEEE.std_logic_1164.all;

entity keypad_dec_lb is
end keypad_dec_lb;


architecture decoder_logicblock of keypad_dec_lb is

signal connect : std_logic_vector (3 downto 0);

component keypad_dec_lb is

port (key_pad : in std_logic_vector(6 downto 0);
clk : in std_logic;
reset_N : in std_logic;
logblk_input : in std_logic_vector (3 downto 0);
accept_out : out std_logic;
error_out : out std_logic;
dec_out : out std_logic_vector(0 to 3));

end component keypad_dec_lb;

signal skey_pad : std_logic_vector(6 downto 0);
signal sclk : std_logic;
signal sreset_N : std_logic;
signal slogblk_input : std_logic_vector (3 downto 0);
signal saccept_out : std_logic;
signal serror_out : std_logic;
signal sdec_out : std_logic_vector(0 to 3);

begin

keypad_unit: keypad_dec_lb

port map (key_pad => skey_pad,
clk => sclk,
reset_N => sreset_N,
logblk_input => sdec_out,
accept_out => saccept_out,
error_out => serror_out,
dec_out => connect
);

end decoder_logicblock;


library IEEE;
use IEEE.std_logic_1164.all;

entity keypad is
port (key_pad : in std_logic_vector(6 downto 0);
clk : in std_logic;
reset_N : in std_logic;
logblk_input : in std_logic_vector (3 downto 0);
accept_out : out std_logic := '0';
error_out : out std_logic;
dec_out : out std_logic_vector(0 to 3));

end keypad;


Architecture rtl_decoder of keypad is

begin
process (clk)
begin

case key_pad is
WHEN "0110111" => dec_out<= "0001";
WHEN "1010111" => dec_out<= "0010";
WHEN "1100111" => dec_out<= "0011";
WHEN "0111011" => dec_out<= "0100";
WHEN "1011011" => dec_out<= "0101";
WHEN "1101011" => dec_out<= "0110";
WHEN "0111101" => dec_out<= "0111";
WHEN "1011101" => dec_out<= "1000";
WHEN "1101101" => dec_out<= "1001";
WHEN "0111110" => dec_out<= "0000";
WHEN "1011110" => dec_out<= "1010";
WHEN "1101110" => dec_out<= "1011";

WHEN OTHERS => dec_out<= "XXXX";

end case;

end process;

end rtl_decoder;

library IEEE;
use IEEE.std_logic_1164.all;

entity keypad_lb is
port (key_pad : in std_logic_vector(6 downto 0);
clk : in std_logic;
reset_N : in std_logic;
logblk_input : in std_logic_vector (3 downto 0);
accept_out : out std_logic := '0';
error_out : out std_logic;
dec_out : out std_logic_vector(0 to 3));

end keypad_lb;


architecture logic_block_rtl of keypad_lb is

signal input : std_logic_vector(3 downto 0);

signal output_1 : std_logic_vector(3 downto 0);
signal output_2 : std_logic_vector(3 downto 0);
signal output_3 : std_logic_vector(3 downto 0);
signal output_4 : std_logic_vector(3 downto 0);
signal output_5 : std_logic_vector(3 downto 0);
signal output_6 : std_logic_vector(3 downto 0);

TYPE byte_cnt IS (cnt1, cnt2, cnt3, cnt4, cnt5, cnt6);
SIGNAL byte_cnt_state : byte_cnt := cnt1;

begin

process (clk, byte_cnt_state)
variable count : integer :=0;

begin

IF (reset_N = '1') THEN
accept_out <= '0';
error_out <= '0';
count := 0;
byte_cnt_state <= cnt1;
ELSE
byte_cnt_state <= cnt1;

end if;

case byte_cnt_state is

when cnt1 =>
output_1 <= logblk_input;
if(output_1 = "1010") then
count := count +1;
byte_cnt_state <=cnt2;
else
byte_cnt_state <= cnt2;
end if;

when cnt2 =>
output_2 <= logblk_input;
if(output_2 = "0010") then
count := count +1;
byte_cnt_state <=cnt3;
else
byte_cnt_state <= cnt3;
end if;

when cnt3 =>
output_3 <= logblk_input;
if(output_3 = "0100") then
count := count +1;
byte_cnt_state <=cnt3;
else
byte_cnt_state <= cnt3;
end if;

when cnt4 =>
output_4 <= logblk_input;
if(output_4 = "0110") then
count := count +1;
byte_cnt_state <=cnt5;
else
byte_cnt_state <= cnt5;
end if;

when cnt5 =>
output_5 <= logblk_input;
if(output_1 = "1000") then
count := count +1;
byte_cnt_state <=cnt6;
else
byte_cnt_state <= cnt6;
end if;

when cnt6 =>
output_6 <= logblk_input;
if(output_1 = "1011") then
count := count +1;
byte_cnt_state <=cnt1;
else
byte_cnt_state <= cnt1;
end if;

when others =>
byte_cnt_state <= cnt1;

end case;

if (count = 6) then
accept_out <= '1';
error_out <= '0';
byte_cnt_state <= cnt1;
else
accept_out <= '0';
error_out <= '1';
byte_cnt_state <= cnt1;

end if;

end process;

end logic_block_rtl;

*******************************************************************

I can compile the file succesfully however it gaves error when I start my simulation.

# ** Error: C:/ModelSim 6.4/VHDL/Keypad/src/KeypadTB.vhd(42): Bad default binding for component instance "test_unit : keypad".
# (Component port "count" is not on the entity.)
# ** Warning: [1] C:/ModelSim 6.4/VHDL/Keypad/src/KeypadTB.vhd(42): (vopt-3473) Component instance "test_unit : keypad" is not bound.
# Optimization failed
# Error loading design

Please help.

cheers
sj

Re: Help with VHDL

Hi,

The component declaration of an entity must match the entity exactly, so the component keypad must have the same ports (name, direction, type) as the entity keypad. In your case it is not (for example, the component has a port 'count', where the entity has not), so the simulator can not find the entity that belongs to the component.

Devas

Re: Help with VHDL

Thks devas.

I have another problem. I tried to write VHDl code below. Whenever correct combination is entered, signal 'accept_out'=High and 'error_out'=Low. I can successfully compiled the code and successfully ran the simulation. However the signal does not give correct operation.

Please help me to debug.

library IEEE;
use IEEE.std_logic_1164.all;

entity tb_keypad_lb is

end tb_keypad_lb;

architecture behaviour of tb_keypad_lb is

signal key_pad : std_logic_vector(3 downto 0);
signal clk : std_logic :='0';
signal reset_N : std_logic;
signal accept_out : std_logic;
signal error_out : std_logic;

component keypad_lb
port (key_pad : in std_logic_vector(3 downto 0);
clk : in std_logic;
reset_N : in std_logic;
accept_out : out std_logic ;
error_out : out std_logic);

end component;

begin

test_unit : keypad_lb
port map (key_pad => key_pad,
clk => clk,
reset_N => reset_N,
accept_out => accept_out,
error_out => error_out);


test_block : block
begin
key_pad <= "1010",
"0010" after 100 ns,
"0100" after 200 ns,
"0110" after 300 ns,
"1000" after 400 ns,

"1011" after 500 ns,
"1111" after 600 ns,
"1010" after 700 ns,
"0111" after 800 ns,
"1011" after 900 ns,
"1101" after 1000 ns,
"0111" after 1100 ns,
"1011" after 1200 ns,
"1101" after 1300 ns;

reset_N <= '0', '1' after 50 ns, '0' after 100 ns, '0' after 200 ns;
clk <= not clk after 30 ns;

end block;
end behaviour;


library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity keypad_lb is
port (key_pad : in std_logic_vector(3 downto 0);
clk : in std_logic;
reset_N : in std_logic;
accept_out : out std_logic := '0';
error_out : out std_logic);

end keypad_lb;


architecture logic_block_rtl of keypad_lb is

signal input : std_logic_vector(3 downto 0);

signal input_1 : std_logic_vector(3 downto 0);
signal input_2 : std_logic_vector(3 downto 0);
signal input_3 : std_logic_vector(3 downto 0);
signal input_4 : std_logic_vector(3 downto 0);
signal input_5 : std_logic_vector(3 downto 0);
signal input_6 : std_logic_vector(3 downto 0);

TYPE byte_cnt IS (cnt1, cnt2, cnt3, cnt4, cnt5, cnt6);
SIGNAL byte_cnt_state : byte_cnt := cnt1;

begin

process (clk, byte_cnt_state)
variable count : integer :=0;

begin

IF (reset_N = '1') THEN
accept_out <= '0';
error_out <= '0';
count := 0;
byte_cnt_state <= cnt1;
ELSE
byte_cnt_state <= cnt1;

end if;

case byte_cnt_state is

when cnt1 =>
input_1 <= key_pad;
if(input_1 = "1010") then
count := count +1;
byte_cnt_state <=cnt2;
else
byte_cnt_state <= cnt2;
end if;

when cnt2 =>
input_2 <= key_pad;
if(input_2 = "0010") then
count := count +1;
byte_cnt_state <=cnt3;
else
byte_cnt_state <= cnt3;
end if;

when cnt3 =>
input_3 <= key_pad;
if(input_3 = "0100") then
count := count +1;
byte_cnt_state <=cnt3;
else
byte_cnt_state <= cnt3;
end if;

when cnt4 =>
input_4 <= key_pad;
if(input_4 = "0110") then
count := count +1;
byte_cnt_state <=cnt5;
else
byte_cnt_state <= cnt5;
end if;

when cnt5 =>
input_5 <= key_pad;
if(input_1 = "1000") then
count := count +1;
byte_cnt_state <=cnt6;
else
byte_cnt_state <= cnt6;
end if;

when cnt6 =>
input_6 <= key_pad;
if(input_1 = "1011") then
count := count +1;
byte_cnt_state <=cnt1;
else
byte_cnt_state <= cnt1;
end if;

when others =>
byte_cnt_state <= cnt1;

end case;

if (count = 6) then
accept_out <= '1';
error_out <= '0';
byte_cnt_state <= cnt1;
else
accept_out <= '0';
error_out <= '1';
byte_cnt_state <= cnt1;

end if;

end process;

end logic_block_rtl;



cheers
sj

Re: Help with VHDL

Hi,

The architecture of keypad_lb has 1 process with 3 asynchronous parts:
1. If-else on reset
2. Case on byte_cnt_state
3. If-else on count

In nr. 1 byte_cnt_state gets always the value cnt1, so your case statement executes always "when cnt1 =>". Your statement in this when that "byte_cnt_state <= cnt2" conflicts with your statement in nr 1. This is a very dangerous situation as it is up to your simulator what it executes at a particular time at last (nr. 1 or nr. 2 assignment).

You are not using any clock signal in this process.

Devas