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First you need to know that, there is only one VERILOG...
You can have a synthesizable or non-synthesizable codes, and it depends on your aim.. If you need a behavioral model, it's aim is for simulation and you can use simulation-purposed codes..
If you need a structural model, you need to take care of your keywords and structure can be synthesized...
I think that, you heard the simulation models that wrote in verilog is normal verilog..
Because, Verilog is suitable for simulation...
the verilog code that can give the RTL schematic or gate level circuit that can be implemented on silicon is synthesisable code where as some syntaxes are in verilog just use for making easy code to simulate design are not going to make actual hardware are non-synthesisable code...
hope clear
if you want to put on hardware you need to write synthesizable code else just for simulation verification use any contexst nd syntax of verilog
thnx. i m doing a project VLSI implementation of image compression on fpga . so for implementing on h/w i need synthesisable verilog. is it right?
i have a code in c .can u suggest me some converter which can convert c to synthesizable verilog code
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