The Layout of Power MOS

power mos layout

Dear All :

I work on DC-DC circuit , I read some paper , And it say the POWER MOS is very critical , Becasue the Size is very big , BuT i don't find the layout , Does anuone know how to do this POWER MOS , or the experiment for the layout ,Please tell me how to do this ?

Thanks

power mos layout guide

I don't know about power MOS, but usually when the transistor is big you use multiple fingers in the layout

pls power dmos

Yes ,Becasue teh Size is very larage, So that the Layout is very critical , And there are many strcutre for this POWER MOS , But I don't what's best , I need the experiment person tell me , How do that ??

layout power pmos

national and maxim have much such application articles for their pruducts.

mos power transistors layout

Dear Tryagain :
Can you give the part number ? Becasue I work on IC design , I need the layout of IC , not board .

powermos layout

Eventhough you get the IC no. from national or maxim, it is not good enough to have a good knowledge on Power MOS layout!

To learn layout better, I think you sholud find someone who is familiar with layout! It is because a good layout designer have done a lot of layout and experience! Better to ask them to guide you....

best mos transistor layout for power

pls ref it:

Do you have the Ebook " The Art of analog Layout " , I have read some thesis , It write I can reference this Power MOS layout , Thanks

looks like alphi`s attachment is not applicable to the question

different layout of power mos depend on your design and the posistion of power mos in the whole layout. The most important perhaps is several rings of power mos.

mitgrace,

When integrating a power mosfet on the die it is necessary to minimize the metal resistance between the transistor active area and the bonding pad. Calculate the sheet rho of the metal through the path from source to drain. Often the metal has more resistance than the mosfet channel

Do you know whether your target process has vertical,
lateral or quasi-vertical DMOS? This would be your choice
for hard switching power MOSFETs. However there is a lot
of "drain engineering" to optimize these, which you would
not want to be your responsibility on a one-shot-to-success
project.

Your best interconnect is going to look like a pine tree. Fat
at the base, skinny at the far end (where, conversely,
the other leg is fat). Many, many fingers. Thick metal
for S/D, collecting from lower-level cross-straps intrasegment.
If you are allowed to fly bondwires into the core this can be a
very significant improvement (all large size power MOSFETs
I have seen, do this for the source bonds).

If you have to favor one terminal for fattest metal, give it
to the source, minimizing gate-source debiasing under
load.

There was a relevant discussion on power device layouts in this thread:

https://www.edaboard.com/threads/150676/

Also, this paper can give some insight into how to simulate metal interconnects and layouts of power devices, calculate Rdson value, analyze current density etc.:

https://www.siliconfrontline.com/fi...d_National_Semiconductor_ISPSD-2010_LV-P4.pdf


The problem is that there are many constraints and considerations in creating power device layouts, and the optimum layout depends on package type, metal resistivities, wirebond resistances, device resistances, etc.

An experienced designer or layout engineer gain this knowledge from an experience, but for a newcomer the learning can be time consuming and painful.