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verilog synthesizeable operators

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naizath12

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is <<(left shift) and >>(right shift) bitwise operators synthesizeable???
 

it is synthesizeable.
a << 3 works well.
a << b is not recommended and will use too much resource.

and you could use this : {a[5:0],3'b0}
it equals to a<<3
 
Yes it's synthesizable but not good for timing. Use the method the previous poster suggested. You probably need to use a big case statement to include all the possible shifting values though.

- Hung
 

Yes it's synthesizable but not good for timing.
Click to expand...
Why? If you are using a variable shift factor, it should be clearly range restricted. But then, a modern design
compiler should be able to minimize the logic. I wouldn't expect different resource requirements for the high level
a << n statement versus a fully decoded case construct.
 

FvM said:
Yes it's synthesizable but not good for timing.
Click to expand...
Why? If you are using a variable shift factor, it should be clearly range restricted. But then, a modern design
compiler should be able to minimize the logic. I wouldn't expect different resource requirements for the high level
a << n statement versus a fully decoded case construct.
Click to expand...

c[31:0] = a[31:0] << b[4:0] means
Code: 
case(b)
    5'h0 : c = a;
    5'h1 : c = {a[30:0],1'b0};
    5'h2 : c = {a[29:0],2'b0};
    .
    .
    .
    5'h1f : c = {a[31],31'b0};
endcase
 

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