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array initialization on separate file in verilog

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naz56

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verilog array initialization

hi everyone :)
can it b possible to initialize array in separate file?
like
/////////////////file(1) define.v //////////
initial
begin

array[0]=8'h56;
array[1]=8'h56;
array[2]=8'h56;
array[3]=8'h56;

end
///////////////////////////////



then in new file named "main.v" i want 2 use "define.v" file here

module kkkk(etc etc);

`include "define.v"


etc etc etc

endmodule

but its nt working...helppppppppppppppppppp
 

verilog parameter array

yes.. you can do it.. but i dont know about assigning it directly but i have used with the parameter. though the end result turns out the same.

parameter a[0]=3;
rather than a[0]=3;

bye

haneet
 

    N

    naz56

    Points: 2
    Helpful Answer Positive Rating
verilog array

its nt working :(


anyone there to help???????????
 

verilog initialize array

are including the define.v in the main .v file??
 

array verilog

YUP HANEET....HELP
 

how to define an array in verilog code

could you put your code here.. i will see wht the trouble is...
 

verilog array assignment

////////////(main.v) file
module main(out1,out2,in);
output [1:0] out1;
output [1:0] out2;
input in;
reg [1:0]out1;
reg [1:0]out2;

reg [1:0] a[0:1];



`include "define.v"
always @(in)

begin
if(in==0)
out1=a[0];
if(in==1)
out2=a[1];
end

endmodule

///////////////////////////////
module stimulus;
module stimulus();
wire [1:0] out1;
wire [1:0] out2;
reg in;
main mm1(out1,out2,in);
initial
begin

# 10 in=0;
#10 in=1;
#10;

end
endmodule

///////////////////////////////////

2nd file
//////////////////define.v file///////////////
parameter a[0]=2'b01;
parameter a[1]=2'b10;
//////////////////////////////////////


plz check...n how can define.v file is used in main.v file...plz quickly help...i will b very thankful 2 u...
 

initialize array verilog

hi Naz,

the 1st thing which you should correct is you have declared the array as reg which should be wire since you are initializing the array outside the always block. and another thing don't use parameter...
use `define or simple assign statement.
another thing you have defined stimulus module twice...

Here is the code:
////////////(main.v) file
module main(out1,out2,in);
output [1:0] out1;
output [1:0] out2;
input in;
reg [1:0]out1;
reg [1:0]out2;

wire [1:0] a[0:1];

`include "define.v"
always @(in)

begin
if(in==0)
out1=a[0];
if(in==1)
out2=a[1];
end

endmodule

///////////////////////////////
module stimulus();
wire [1:0] out1;
wire [1:0] out2;
reg in;
main mm1(out1,out2,in);
initial
begin

# 10 in=0;
#10 in=1;
#10;

end
endmodule

2nd file
//////////////////define.v file///////////////
//assign a[0]=2'b01;
//assign a[1]=2'b10;

OR

`define a[0] 2'01;
`define a[1] 2'10;
/////////////////////////////////////////////////

you can use either assign statement or `define. both will work

Haneet
 

    N

    naz56

    Points: 2
    Helpful Answer Positive Rating
using a module in another file verilog

again not working
:cry: :cry: :cry: :cry:

n output in ModelSim is:

#in=x,out1=x,out2=x
# in=0,out1=x,out2=x
# in=1,out1=x,out2=x


:cry:

Added after 23 minutes:

hello anybody there 2 help me out?????????????????????????
this is output when using "assign "

in=x,out1=z,out2=z
# in=0,out1=z,out2=z
# in=1,out1=z,out2=z

Added after 48 minutes:

i think when we use `define then there iz no need of `include directive..
 

verilog include defines.v

hey naz.. i thght i resolved it so didnt check this thread..

whtz the prob u r facing?? the code which i pasted is working perfectly...
i tried it out...

haneet
 

    N

    naz56

    Points: 2
    Helpful Answer Positive Rating
initializing array to 0 in verilog

which simulator u r using? i m using modelsim5.7..but nahi chal raha.. error is macro module iz missing... :(
 

initialize array in verilog

i am using vcs....
but i dn tthink there shld be any problem if 1 tool is supporting...
by the way r u using the student version of modelsim??

haneet
 

initialize arrays in verilog

its a cracked version :cry:
 

verilog how to put parameters in separate file

i am sure if it has the feature to support the directives...

y dont u try dwnldng the student version and then try??

itz working on my tool so i dnt see y itshldnt work on urs...

haneet
 

    N

    naz56

    Points: 2
    Helpful Answer Positive Rating
verilog array initial

okz :(:| :cry:
 

I have tried something similar but the data dat i am passing through the define clause appears as 'zzzzzz' when simulated in modelsim

please help
 

Any body help me to iniatializing array........i do'nt get the output pls help me......


i used the array within always block and case statement.
it is not showing error while synthesizing but no output is shown.
 

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