Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

32 bit adder - implementation in Verilog for RTL

Status
Not open for further replies.
R

rockskuller

Junior Member level 2
Joined
Apr 7, 2009
Messages
21
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,408
Adder

I wish to design a 32 bit adder. So result at the max can be 33 bits. But my output is 32 bits. Hence I should conditionally shift by one bit if the carry is set when 32nd bit is added. How can this be implemented in Verilog for RTL?
 

Re: Adder

Checkout this..........
Code: 
module adder32(
   // Outputs
   result, 
   // Inputs
   a, b
   );
   input[31:0] a;
   input[31:0] b;
   output [31:0] result;
   wire [32:0] sum = {1'b0,a} + {1'b0,b};
   assign      result = sum[32] ? sum[32:1]: sum[31:0];
endmodule // adder32
 
why output is only 32 bits? and why the result should be shifted

result = sum[31:0];
carry = sum[32];

if shift, the result seems be averaged
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top