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Why control signals in DRAM active low?

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sita

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description control signal dram

Hi all,

I have one basic doubt in DRAM.

As we see in DRAM, all command & control signals

Row Address Strobe
Column Address Strobe
Output Enable
Write Enable

are active low. What is the reason for this?

Logically it proves to be advanatgeous to be active high, as logic high voltage need to be given as and when required and is power saving.

Same is the concept when we notice, many microprocessors have active low reset.

Please answer my doubt, if anyone knows it.......

If any one have some good material on memory, (DRAM, SDRAM, DDR technology), can you please post the same?

Thanks,
sita
 

what are active low signals

as a mater of fact all control signals are active low. the high impedance control lines have stray capacitance which could be charged by noise on nearby signals. if the signal voltage moves above TTL threshold it can initiate the control action. on the other hand on active low signal the trigger will only come when the line is pulled low by the controller.

hock
 

ttl+active low signals

It's a pure TTL legacy, but doesn't hurt with CMOS. Just regard it as a convention, that has been adapted by the CMOS world from the beginning. It possibly will survive the knowledge of TTL existence.
 

ttl active low

Thanks folks for your valuable reply.

I understood Mr/Ms Hock's viewpoint. But does the stray caps appearing in control line will be so high that can it can cross min threshold for high voltage(say, 2V in case of LVTTL logic). It's out of my curiosity that I am asking, how can you justify the statement that " control lines have very high impedance"?

But Mr/Ms. FvM I did not understand what you meant. Can you clarify more on the same?
 

why most signals are active low

the ttl input impedance is in 100k to 10 m ohms. also the output impedance of the driver is in 10K range. so the minimum impedance to the ground for the track is more then 10K. this along with a track and driver and receiver capacitance of few 100 pF will have a time constant of few micro second.


hock
 

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    sita

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dram active time

Thank You Hook.

I have some more doubts in memory. Posted in this link:-


Actually I am struggling to get knowledge in SSTL logic used in DDR. Can you help me if you have any good reading material?

I shall be greatful to you, if so.

Thanks once again,
sita
 

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