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Timing delays - compiler directive delay_mode_zero

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sujithchakra

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delay_mode_zero

Hi,

I have a synthesized design(netlist) which I simulated using Cadence NC-Verilog using compiler directive +delay_mode_zero and functionality seemed to be correct. Now I am using Xilinx ISE to synthesize and simulate the design. I have two questions here.


1)How can I simulate the synthesized design(netlist) ignoring the timing delays in Xilinx ISE because +delay_mode_zero compiler directive is not supported in Xilinx.

2)What should I do to make the design work when I simulate the netlist without ignoring the timing delays?

Please help.

Thanks,
Sujith Chakra
 

Timing delays

Answering 2nd Question,

- Take a design that meets design,
- backannotate SDF ( generating by STA tools) into simulator
- ensure that standard cell models have all the arcs/checks in specify block
- enable timing checks in simulator ( so that simulator corrupts output as per checks mentioned in specify block).
 

Re: Timing delays

Thank you rjainv for the quick response. I did not understand "Take a design that meets design" in your reply. Can you be more clear? which simulator are you talking about? Is it Xilinx ISE? I am trying to simulate it using Xilinx ISE 10.1 to implement it in an FPGA. Please help.

Sujith Chakra
 

Re: Timing delays

I meant, design should meet timing in STA tools, otherwise you would anyway see those violations in your simulations ( after annotating SDF generated by same STA tools) and simulation would fail.

Simulator can be any - VCS/NC-verilog/Modelsim etc, All support SDF backannotation, only the switches/options to do so are different.

I haven't worked in xilinx-ISE, but I am hoping that it would also support SDF backannotation. But since its a integrated tool, it might give you smarter way of simulating timing delays.
 
Re: Timing delays

Thank you for the reply rjainv. I shall try doing what you mentioned and see.

Thanks,
Sujith Chakra
 

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