Battery charger IC is burned down, need your help!

Hi all,
My chip is burned down, it was burned after a long operation during tests. It's a 1A charger IC. I have tested several tens chips, but 2 were damaged. I saw Supply current is current limited by my setting(2A), VBAT current is ~30mA, and then chip was burned down.
1) Could you help me to figure out what're the causes in your experience?
2) Will latch-up result in this condition? When the circuit might cause latch-up condition, will all chips fabricated latched-up?
3) When lath-up condition happens in some chip, will this chip be damaged and never be powered up or never works?
Thanks for your help.

Can you tell us what type of chip you are referring to?
Perhaps a schematic would help, too.

It's a Li-ion battery charger IC, with input voltage 5V, BAT Fast charge current 1A, VCH=4.2V.
Thanks a lot!

Hi Welton

For investigating latch-up there are 2 standardized tests used throughout the industry: Both tests are described in the JEDEC78A document, available from the Jedec website: https://www.jedec.org/download/search/jesd78A.pdf

1. Bias the chip like during normal function. Add pulse on top of the supply potential. Parasitic devices or ESD protection elements might get triggered by this pulse leading to latch-up situation. Typically the IC should be able to sustain 1.5xVdd without latch-up. This level might be increased for IC's with inductive connections

2. Bias the chip like before but this time inject current pulse into the IO's. Typically a level of 100mA must be tolerated without latch-up. For harsh (automotive, industrial) environments levels of 300mA are used.

Results for both tests should be displayed on the datasheet of the IC vendor.

Watch-out: Most latch-up problems are worse at elevated temperature.

Besides those standardized tests there are some other test conditions that strongly vary per application or IC/OEM company. E.g. it is typical in the LCD panel drivers to apply so-called 'CCL' - Charged Capacitor Latch-up tests. This basically is similar to applying a Machine Model (MM) Electrostratic Discharge (ESD) stress, while the IC is biased. Other names for similar tests are V-latch, AC-latch-up. In some other industries, OEM's may use a so-called 'ESD ZAP-GUN' to apply system level ESD stress at the finalised system during operation. Information about these test types are only seldom mentioned on datasheets since these are not standardized tests.

Maybe this is what happened to 2 out of the 10 chips tested: Maybe these 2 chips received an ESD stress during the long operation tests. This is possible when there was human or machine interaction closeby the test setup during the tests.

For solving your problem...
- Do you have an idea about the failure location. Is it possible for you to perform physical failure analysis? Maybe the IC vendor might provide help here.
- Do you have an idea about the ESD protection approach used in the IC?
- Is it possible to stabilize the supply potential by adding a large capacitance (uF) across Vdd-Vss of the IC?

Thank you ESDsolution,
The situation is, when I was doing short circuit TESTs, the IC is biased at trickle condition.
1) VIN=+5V, VBAT=0V(in trickle charge condition), TEMP=1.5V(normal condtion).
2) I used a metal wire to short VBAT and TEMP, there is a large current(2A, current limited by 1.5V supply) flow into E-load. This should be normal condition because E-load should sink the current.
3) When I try to touch on and off the metal wire(to let the VBAT and TEMP switch between short and open condition), IC was burned down. I de-cap the IC and found the damaged place is near the Source of the power PMOS.
I have no idea why it happened because during normal operations, the current is more then 1A, and the chip works well.
Please help me.
Thank you very much!