[10 pts] Resetting Circuits

Hi all,

Suppose you have an IC circuit and you plan to use it. Obviously the circuits need to be feed with power supply to run. Here starts my doubts !

As far as I know, at the moment when the IC is feed with the power supply it will operate and its behaviour will depend on the initial signal's state of the logic that it encompass so the circuit will not operate correctly. For that reason the reset of the circuit is mendatory after powering the circuit. My question is
Who resets the circuit ? Does the discussed circuits contain a controller that resets the circuit each time the circuit is powered ?

I thougth about another answer that can reply to my question:
Is the circuit designed having in mind the initial values (power on reset) of the gates forming the circuit.

Please help.

Your initial asumption is wrong.

All IC's/circuitry does not need to be reset.

But assuming you are working with a system which requires a reset (or initial conditions applied to it, which is what you are really talking about), then this can be applied in many ways and is entirely up to the designer which is used.

Thanks Old Nick for your prompt reply,

Old Nick said:

Your initial asumption is wrong.
All IC's/circuitry does not need to be reset

Click to expand...

I dont get that. I thing that you are talking about non logic circuit like pll, amplifyers....
How does digital IC dont need to be reset.

In fact I designed a circuit using asynchronous dff and some logics. The dff outputs 1 at power on. In order to operate correctly the DFF output must be reset, so the circuit need to be reset.
How can I solve this problem ?

Hi,
Power-On-Reset is mandatory only for circuits containing Sequential logic involving Memory circuits. For circuits containing Combinational logic implementing Boolean logic, the outputs depend on inputs and there is no need for any Power-On-Reset. For Sequential Logic you use an external Reset circuit to bring it to a known specific state at start.

Regards,
Laktronics

mouzid said:

Thanks Old Nick for your prompt reply,

Old Nick said:

Your initial asumption is wrong.
All IC's/circuitry does not need to be reset

Click to expand...

I dont get that. I thing that you are talking about non logic circuit like pll, amplifyers....
How does digital IC dont need to be reset.

Click to expand...

No I wasn't. But you did post this in the analogue forum

A bank of NAND gates for instance, needs no reset since the output depends on the current input and not the last one etc.

Assuming that your circuit needs and external reset there are many ways to do it. Here are two examples.... resistor with one side going to +volts and the other side going into the input of a schmitt trigger gate with a small cap going to 0v between the resistor and the input.
Or you could have a counter running that triggers reset at a certain count. If this is not what you are asking for then I suggest that you show us the circuit and then we can give you a better answer

laktronics said:

Hi,
Power-On-Reset is mandatory only for circuits containing Sequential logic involving Memory circuits. Laktronics

Click to expand...

Rightly laktronics,

In my case I have a queue to store data.

Use a debounced button/switch attached to all the resets on your circuit (and VDD or GND) and if some elements require opposite logic for a reset then place inverters between the switch and the reset).

You can then reset the circuit with the press of a button.

And even in the case you've just mentioned, a reset is not mandatory as several clock cycles with known data would flush the memory elements anyway.

Old Nick said:

Use a debounced button/switch attached to all the resets on your circuit (and VDD or GND) and if some elements require opposite logic for a reset then place inverters between the switch and the reset).

You can then reset the circuit with the press of a button.

And even in the case you've just mentioned, a reset is not mandatory as several clock cycles with known data would flush the memory elements anyway.

Click to expand...

I need that the reset happen automatically at power on. Frankly, I thouth about using a counter like stated by davidgrm and I think that I'll go in that direction even if I find it a bad (=very primitive)solution.
I find this issue very important and it is worth to be detailed in my dissertation. Can I do it ? I'm hesitating coz some people consider alway that initial conditions are ok when they talk about IC design.

In other side, I didnt expect to find this problem when I designed the circuit since nobody talked about that In all the IC design book that I read. Realy this is strange, how all this autors ignored to talk about this important issue without it the circuits that they teaching us their design would be useless.

davidgrm said:

Assuming that your circuit needs and external reset there are many ways to do it. Here are two examples.... resistor with one side going to +volts and the other side going into the input of a schmitt trigger gate with a small cap going to 0v between the resistor and the input.

Click to expand...

Thanks davidgrm,
Could you please explan the purpuse of your circuit. Is it to generate a certain delay, I mean generate an edge ( rise or falling edge dependig on our reset) so that when the circuit is powered, the signal is generated to the reset after a short time ?

just replace the push-button for say an RC circuit and a comparator, so that after some time (allowing for the circuitry to settle), the RC element charges to a value the comparator switches to a high (or whatever), and use that as your reset pulse. This will not fire again unless you power down and power up.

There's bound to be better ways of doing this, but that's the first one that popped into my head.

You'll either need some edge detection to create a pulse of a certain length after the comparator, or another RC-comparator circuit with a larger time constant to turn of an SR(or whatever) to create the pulse width.

The circuit that I describe with the schmitt trigger is a fairly standard way of creating a delay. It will work fine as a reset. The cap charges up via the resistor to the point where the gate switches, being a schmitt trigger it will give a clean change on the output regardless of how slowly the input rises (within reason i guess). The counter circuit is also a fairly common concept. The one advantage of a counter is that having multiple outputs you can reset different IC's in a sequence if required. As I said there are many ways of doing this. I have worked on equipment that just used 2 capacitors , 2 transistors , 3 resistors and a zener diode. This not only gave a power on reset but also reset when the voltage dropped below a certain minimum. There are also special reset IC's available. But for your circuit if you really feel that it is needed I would simply use the schmitt trigger as detailed above. Something like a 74hc14 would be fine - just remember to connect all the unused inputs to 0v / 5v

BTW I am assuming this is a discreet circuit that you have and not one in a CPLD or FPGA? If it is the latter then I would suggest the counter which would be in the same device

RC tied to input of schmitt trigger IC. http://www.scienceprog.com/schmitt-trigger-vs-simple-inverter/