soloktanjung
Full Member level 6
xst 528 multi-source in unit
Hi friends,
I've got this error while doing synthesis and stuck for about a week. If anybody has any idea, please point me out what correction should I made in the code.
I'm using Xilinx ISE 9.2i.
The errors say:
Thanks in advance.
Hairo
Hi friends,
I've got this error while doing synthesis and stuck for about a week. If anybody has any idea, please point me out what correction should I made in the code.
I'm using Xilinx ISE 9.2i.
Code:
`timescale 1ns / 1ps
module stage4(clk,
rst,
s3a,
s3b,
s3c,
s3d,
s3e,
s3f,
s3g,
s3h,
data_out0,
data_out1,
data_out2,
data_out3,
data_out4,
data_out5,
data_out6,
data_out7);
input clk, rst;
input signed [15:0] s3a, s3b, s3c, s3d, s3e, s3f, s3g, s3h;
output signed [16:0] data_out0, data_out1, data_out2, data_out3;
output signed [16:0] data_out4, data_out5, data_out6, data_out7;
// 10 add/sub, 8 shift
reg [2:0] count8_adder_stage4;
wire [2:0] select1_stage4;
wire [1:0] select2_stage4;
wire add1, add2;
always@(posedge clk, posedge rst)
begin
if(rst)
count8_adder_stage4<=0;
else if(count8_adder_stage4==5)
count8_adder_stage4<=0;
else
count8_adder_stage4<=count8_adder_stage4+1;
end
assign select1_stage4 = count8_adder_stage4;
assign select2_stage4 = count8_adder_stage4[1:0];
assign add1 = (select1_stage4==0) || (select1_stage4==5);
assign add2 = (select1_stage4==2);
// 2 mux for input to the adder.
// (* signal_encoding = "user" *)
reg signed [16:0] data_out0, data_out1, data_out2, data_out3;
reg signed [16:0] data_out4, data_out5, data_out6, data_out7;
reg signed [15:0] mux1_stage4, mux2_stage4, mux3_stage4, mux4_stage4;
reg signed [15:0] s3d_3, data_out6_3;
wire signed [15:0] data_out0_1, s3d_1, s3d_2, s3b;
wire signed [15:0] data_out6_1, data_out6_2;
assign data_out6_1 = data_out2>>>1;
assign data_out6_2 = data_out2>>>3;
assign s3d_1 = s3d>>>1;
assign s3d_2 = s3d>>>3;
assign data_out0_1 = data_out0>>>1;
always@(select1_stage4, s3a, data_out0_1, s3d_3, s3d_1, data_out6_3, data_out6_1)
begin
case(select1_stage4)
3'd0: mux1_stage4=s3a;
3'd1: mux1_stage4=s3d_1;
3'd2: mux1_stage4=data_out0_1;
3'd3: mux1_stage4=s3d_3;
3'd4: mux1_stage4=data_out6_1;
3'd5: mux1_stage4=data_out6_3;
default:mux1_stage4=0;
endcase
end
always@(select1_stage4, s3b, s3d_2, s3c, data_out6_2, s3d)
begin
case(select1_stage4)
3'd0: mux2_stage4=s3b;
3'd1: mux2_stage4=s3d_2;
3'd2: mux2_stage4=s3b;
3'd3: mux2_stage4=s3c;
3'd4: mux2_stage4=data_out6_2;
3'd5: mux2_stage4=s3d;
default:mux2_stage4=0;
endcase
end
wire signed [16:0] add1_stage4;
assign add1_stage4 = add1?(mux1_stage4 + mux2_stage4):(mux1_stage4 - mux2_stage4);
always@(posedge clk, posedge rst)
begin
if(rst)
begin
data_out0<=0;
data_out4<=0;
data_out6<=0;
data_out2<=0;
s3d_3<=0;
data_out6_3<=0;
end
else
begin
case(select1_stage4)
3'd0: data_out0<=add1_stage4;
3'd1: s3d_3<=add1_stage4;
3'd2: data_out4<=add1_stage4;
3'd3: data_out6<=add1_stage4;
3'd4: data_out6_3<=add1_stage4;
3'd5: data_out2<=add1_stage4;
default:{data_out0, data_out4, s3d_3, data_out6, data_out6_3, data_out2}<=0;
endcase
end
end
wire signed [15:0] s3h_1, s3g_1;
reg signed [15:0] s3g_3;
wire signed [15:0] data_out5_1;
assign s3h_1 = s3h>>>3;
assign s3g_1 = s3g>>>3;
assign data_out5_1 = data_out5>>>1;
always@(select2_stage4, s3e, s3g, s3f)
begin
case(select2_stage4)
3'd0: mux3_stage4=s3e;
3'd1: mux3_stage4=s3g;
3'd2: mux3_stage4=s3f;
3'd3: mux3_stage4=s3g;
default:mux3_stage4=0;
endcase
end
always@(select2_stage4, s3h_1, s3g_1, s3g_3, data_out5_1)
begin
case(select2_stage4)
3'd0: mux4_stage4=s3h_1;
3'd1: mux4_stage4=s3g_1;
3'd2: mux4_stage4=s3g_3;
3'd3: mux4_stage4=data_out5_1;
default:mux2_stage4=0;
endcase
end
wire signed [16:0] add2_stage4;
assign add2_stage4 = add2?(mux3_stage4 + mux4_stage4):(mux3_stage4 - mux4_stage4);
always@(posedge clk, posedge rst)
begin
if(rst)
begin
s3g_3<=0;
data_out3<=0;
data_out5<=0;
data_out7<=0;
end
else
begin
case(select2_stage4)
3'd0: data_out7<=add2_stage4;
3'd1: s3g_3<=add2_stage4;
3'd2: data_out5<=add2_stage4;
3'd3: data_out3<=add2_stage4;
default:{data_out7, s3g_3, data_out5, data_out3}<=0;
endcase
end
end
always@(posedge clk, posedge rst)
begin
if(rst)
data_out1<=0;
else
data_out1<=s3h;
end
endmoduleThe errors say:
Code:
ERROR:Xst:528 - Multi-source in Unit <stage4> on signal <mux2_stage4<15>>
Sources are:
Signal <_n0000<15>> is assigned to logic
Signal <mux2_stage4<15>> in Unit <stage4> is assigned to GND
ERROR:Xst:528 - Multi-source in Unit <stage4> on signal <mux2_stage4<14>>
Sources are:
Signal <_n0000<14>> is assigned to logic
Signal <mux2_stage4<14>> in Unit <stage4> is assigned to GND
ERROR:Xst:528 - Multi-source in Unit <stage4> on signal <mux2_stage4<13>>
Sources are:
Signal <_n0000<13>> is assigned to logic
Signal <mux2_stage4<13>> in Unit <stage4> is assigned to GND
ERROR:Xst:528 - Multi-source in Unit <stage4> on signal <mux2_stage4<12>>
Sources are:
Signal <_n0000<12>> is assigned to logic
Signal <mux2_stage4<12>> in Unit <stage4> is assigned to GND
ERROR:Xst:528 - Multi-source in Unit <stage4> on signal <mux2_stage4<11>>
Sources are:
Signal <_n0000<11>> is assigned to logic
Signal <mux2_stage4<11>> in Unit <stage4> is assigned to GND
ERROR:Xst:528 - Multi-source in Unit <stage4> on signal <mux2_stage4<10>>
Sources are:
Signal <_n0000<10>> is assigned to logic
Signal <mux2_stage4<10>> in Unit <stage4> is assigned to GND
ERROR:Xst:528 - Multi-source in Unit <stage4> on signal <mux2_stage4<9>>
Sources are:
Signal <_n0000<9>> is assigned to logic
Signal <mux2_stage4<9>> in Unit <stage4> is assigned to GND
ERROR:Xst:528 - Multi-source in Unit <stage4> on signal <mux2_stage4<8>>
Sources are:
Signal <_n0000<8>> is assigned to logic
Signal <mux2_stage4<8>> in Unit <stage4> is assigned to GND
ERROR:Xst:528 - Multi-source in Unit <stage4> on signal <mux2_stage4<7>>
Sources are:
Signal <_n0000<7>> is assigned to logic
Signal <mux2_stage4<7>> in Unit <stage4> is assigned to GND
ERROR:Xst:528 - Multi-source in Unit <stage4> on signal <mux2_stage4<6>>
Sources are:
Signal <_n0000<6>> is assigned to logic
Signal <mux2_stage4<6>> in Unit <stage4> is assigned to GND
ERROR:Xst:528 - Multi-source in Unit <stage4> on signal <mux2_stage4<5>>
Sources are:
Signal <_n0000<5>> is assigned to logic
Signal <mux2_stage4<5>> in Unit <stage4> is assigned to GND
ERROR:Xst:528 - Multi-source in Unit <stage4> on signal <mux2_stage4<4>>
Sources are:
Signal <_n0000<4>> is assigned to logic
Signal <mux2_stage4<4>> in Unit <stage4> is assigned to GND
ERROR:Xst:528 - Multi-source in Unit <stage4> on signal <mux2_stage4<3>>
Sources are:
Signal <_n0000<3>> is assigned to logic
Signal <mux2_stage4<3>> in Unit <stage4> is assigned to GND
ERROR:Xst:528 - Multi-source in Unit <stage4> on signal <mux2_stage4<2>>
Sources are:
Signal <_n0000<2>> is assigned to logic
Signal <mux2_stage4<2>> in Unit <stage4> is assigned to GND
ERROR:Xst:528 - Multi-source in Unit <stage4> on signal <mux2_stage4<1>>
Sources are:
Signal <_n0000<1>> is assigned to logic
Signal <mux2_stage4<1>> in Unit <stage4> is assigned to GND
ERROR:Xst:528 - Multi-source in Unit <stage4> on signal <mux2_stage4<0>>
Sources are:
Signal <_n0000<0>> is assigned to logic
Signal <mux2_stage4<0>> in Unit <stage4> is assigned to GNDThanks in advance.
Hairo
