ktsangop
Junior Member level 1
Hi everybody!
Could someone please explain to me why a simulation that is correct in altera quartus isn't in modelsim?
I have quartus 7.2 web ed. and modelsim 6.2b (NOT altera version).
I ran a simulation based on a waveform file i created in quartus and then i exported the report to a verilog test file (*.vt)
I loaded the test file into modelsim and ran the vector_test and it didn't succed. I tried both functional and timing tests.
I also tried to code my own testbenches but none of them worked.
Is it because quartus is using specific device characteristics like gate delays etc. and modelsim doesn't?
Thanks in advance!
Could someone please explain to me why a simulation that is correct in altera quartus isn't in modelsim?
I have quartus 7.2 web ed. and modelsim 6.2b (NOT altera version).
I ran a simulation based on a waveform file i created in quartus and then i exported the report to a verilog test file (*.vt)
I loaded the test file into modelsim and ran the vector_test and it didn't succed. I tried both functional and timing tests.
I also tried to code my own testbenches but none of them worked.
Is it because quartus is using specific device characteristics like gate delays etc. and modelsim doesn't?
Thanks in advance!