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how to simulate

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coolstuff07

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Hi,

I have a standard diode connected ESD. I want to know how to simulate in spice/spectre. Please any one help me how to fine parasitic BJTs and snap back characteristics in it.

Bye
 

spice esd

eds simulation in spice-spectre is quite difficult because you must have quite good models of the esd device, which I never got during my profession. It is also not necessary since a full snap-back will destroy your ic.
Furhter ESD simulation are made with device simulators.
I made simulation once for an heat estimation with a simple model of the chip and sometimes I use a behavioral current source modeling the exponential start of the snap-back because some spec issues were critical in terms of safety.

Hope I could help you.

BR
 

simulating for esd

Any one help me further
 

spectre snapback devices

hello,in some book it told me that if the esd device is
working on NB_MODEL,then we could simulate it with
simple MODEL,if the device is working on the snapback ,then we have to add anther ESD_MODEL;
by far,there are many software on esd ,you may refer them
 

spice esd simulations

there are many software on esd ,you may refer them
Click to expand...
If there are many name couple of them.
 

can esd performance be simulated

Hi

If you are using RC triggered (bigFet) MOS devices as the power cells and just diodes at the IO's then you should be able to simulate ESD with Spice/Spectre without adding additional models for snapback. The idea of this approach is that the bigfet MOS is shunting the current in MOS mode, not snapback.

However, you should verify the voltage levels at the different points in the design. For instance the pad voltage at the IO's can still reach high voltage levels, higher than the trigger voltage of output drivers due to resistivity of the busline or diodes for instance. This 'breakdown information' for the sensitive nodes can be used to optimize placement and sizing of the ESD devices. Look for technical publications from Freescale at the EOS/ESD sympoisum (Stockinger, Michael - Miller, James W.). These publications provide first clues in simulating this kind of protection concept. Beware that most of the actual ESD clamps are proprietary and patented and cannot be copied for commercial use!

If you want to rely on snapback based clamps then simulation with spice-based tools is not easy at all. Personally I would not trust anyone claiming predictability of ESD performance. Setting up a correct model for the snapback of BJT's is a research topic. If the foundry cannot provide models then the best approach would be to rely on the preferred foundry partner for ESD. The person/company that provided the ESD solutions for your process technology can probably help you with models, rules and review to increase the likelyhood of a pass-first-time. Some ESD providers have simulation tools optimized for foundry nodes.

Never trust an ESD provider that claims to reach your ESD specification without them knowing your circuit/IO!
 
snapback simulation in sdevice

Absolutely well answer!! :p
 

Re: can esd performance be simulated

ESDSolutions said:
Hi

If you are using RC triggered (bigFet) MOS devices as the power cells and just diodes at the IO's then you should be able to simulate ESD with Spice/Spectre without adding additional models for snapback. The idea of this approach is that the bigfet MOS is shunting the current in MOS mode, not snapback.

However, you should verify the voltage levels at the different points in the design. For instance the pad voltage at the IO's can still reach high voltage levels, higher than the trigger voltage of output drivers due to resistivity of the busline or diodes for instance. This 'breakdown information' for the sensitive nodes can be used to optimize placement and sizing of the ESD devices. Look for technical publications from Freescale at the EOS/ESD sympoisum (Stockinger, Michael - Miller, James W.). These publications provide first clues in simulating this kind of protection concept. Beware that most of the actual ESD clamps are proprietary and patented and cannot be copied for commercial use!

If you want to rely on snapback based clamps then simulation with spice-based tools is not easy at all. Personally I would not trust anyone claiming predictability of ESD performance. Setting up a correct model for the snapback of BJT's is a research topic. If the foundry cannot provide models then the best approach would be to rely on the preferred foundry partner for ESD. The person/company that provided the ESD solutions for your process technology can probably help you with models, rules and review to increase the likelyhood of a pass-first-time. Some ESD providers have simulation tools optimized for foundry nodes.

Never trust an ESD provider that claims to reach your ESD specification without them knowing your circuit/IO!
Click to expand...

This suggestion was valuable indeed, but i was looking for something more of an explanation for my work if possible.

I am using Dongubu hi-tek foundry for my design, this foundry provides the ESD components with snap-back characteristics. If in this case would it be possible to simulate the ESD circuits in SPECTRE, since they provide us the schematic model of various developed ESD components.
 

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