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FIFO with quartus megawizard

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heythem2008

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Hi, this is the first time that i participate in this forum and i hope that u can help me.
I have created a FIFO with the Megawizard of QUARTUS II.
I have used a double clock FIFO with 2 bit input, a write_request, a read_request, write_empty and read_empty signals.
I tried to simulate i have seen how the write empty has changed but my problem that i cant read the data from the FIFO (output)
I join my schematic and the simulation to give me your help
Thank you.
 

1.do not gate clocks with *empty flag rather but if you want for any reasons
to do so think carefully what is the ACTIVE level of your gating signal;

2.if I guess correctly what you try to achieve - connect wrreq to (not)wrfull
and rdreq to (not) rdempty;
 

FIFO with qu(at)rtus megawizard

but i don't use the wrfull i want just use the wrempty and rdempty, Morover i think the problem is due to the read clock
 

Re: FIFO with qu(at)rtus megawizard

heythem2008 said:
but i don't use the wrfull i want just use the wrempty
and rdempty
Click to expand...
well... if you want - just try;
but may be it's more important what functionality you need,
then what you want to use ?

heythem2008 said:
Morover i think the problem is due to the read clock
Click to expand...
add to your simulator 'rdclk' and 'wrclk' of the fifo and you will see where
the problem is;
 

FIFO with qu(at)rtus megawizard

in fact my input is the output of an ADC i want to get this signal, save it in my fifo then get back the samples and send them to the pc via rs232
i work on altera startix board

for the clock i have 2 clocks but i didnt find the problem
 

FIFO with qu(at)rtus megawizard

thank you, but i didnt understand how do u have get the wrclk and rdclk? and usually the output is not availble

Added after 1 minutes:

i mean thatther is no value in the q output
 

double click on the field with signals name [at the right];
- click 'node finder'
- in the field "Filter" choose: Post-compilation, in "Name" leave '*'
- click 'List
and then find your signals

Added after 2 minutes:

forgot - compile your fifo and choose "simulation mode - timing" in settings
 

FIFO with qu(at)rtus megawizard

sorry if i m bothering you
firstly,does my shematic allow me to get my purpose?
if not can you help me to obtain a good one.
 

Re: FIFO with qu(at)rtus megawizard

heythem2008 said:
does my schematic allow me to get my purpose?
if not can you help me to obtain a good one.
Click to expand...
your schematic is wrong from logical point of view, so it's not good for any
purpose, but if you can put your requirements certainly we will find a solution;
 

FIFO with qu(at)rtus megawizard

ok, i want use a fifo to save the samples obtained from my 8bits adc.
then get back this samples and send them to the PC via an UART RS232
ok the second part(UART RS232) its not necessary ihave the module
for the first one i want write all samples in the fifo (128 samples) until she become full. in this moment is tart reading data from fifo
 

Re: FIFO with qu(at)rtus megawizard

heythem2008 said:
ok, i want use a fifo to save the samples obtained from
my 8bits adc/.../
Click to expand...
it's not so important what is your data source and receiver,
the control signals sequence has an influence on the solution;

so - your adc generates a signal 'data_ready' with data of course
for 128 clock samples, or generates 'data_ready'&data continuously
but you need to 'cut-off' 128 slice, other ?
on the other side - do you really need to wait with data transfer
until fifo is full or can start transmission in parallel to writing ?
other situation ?
 

FIFO with qu(at)rtus megawizard

for the data i want cut off with 128 samples my adc is 80Msps.
and for the reception for the moment i really need when the fifo is full to start reading

Added after 1 hours 5 minutes:

ok, finally i have found the shema necessary to recieve my information
now the problem is in the delay of recienvieng
 

heythem said:
/.../cut off with 128 samples my adc/.../
for the reception i need when the fifo is full to start reading
Click to expand...
very simple solution assuming write and read clock is the same:
create an 8 bit cnt[7:0] counter which runs with the same clock as fifo,
connect cnt[7] - the 8th bit of the counter - as rdreq, and the same
cnt[7] inverted as wrreq;

if your read & write clocks are independent, different,
you will need 2 counters and a very simple FSM;
--
write:
38_1216159087.jpg


read:
39_1216159120.jpg
 

========
the problem is in the delay of receiving
Click to expand...
forgot it ...
when you create a fifo you have to decide if the fifo should be
'show-ahead type' or not;
turning ON this mode means the first written word appears at the
output as soon as possible regardless of the read-reqest signal state,
when OFF fifo outputs its content after seeing read-request active;
 
FIFO with qu(at)rtus megawizard

ok thank you for this, i will try it now and i will tell you what happen with me

Added after 21 minutes:

oui ça marché

Added after 1 minutes:

sorry, i forgot the language
i mean, ok it works, the delay of recievieng is now correct
 

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