277897909
Junior Member level 2
I am testing a chip of a clock circuit.
At first it works normally,but later on I found the output(of a chain os inverter buffer) is appear as an DC clamped at some 1.9V.(Vdd=3.3).
I also notice that the clamped voltage is changing according to Vdd.
In the chip I did no ESD for the output inverter buffer.
So anybody ever encounter such problem?
Is it a phenomena of breakdown or else?
Thanks and all the best regards!
At first it works normally,but later on I found the output(of a chain os inverter buffer) is appear as an DC clamped at some 1.9V.(Vdd=3.3).
I also notice that the clamped voltage is changing according to Vdd.
In the chip I did no ESD for the output inverter buffer.
So anybody ever encounter such problem?
Is it a phenomena of breakdown or else?
Thanks and all the best regards!