Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Detailed question about some problematic cases of PLL usage

Status
Not open for further replies.
AdvaRes

AdvaRes

Advanced Member level 4
Joined
Feb 14, 2008
Messages
1,163
Helped
113
Reputation
220
Reaction score
51
Trophy points
1,328
Location
At home
Activity points
7,442
Hi members,

I'm using the book of Gadner as a reference to understand how PLL is designed and how works its differents blocks. However when I tried to understand in depth these issues, I noticed that the book as well as the majority of the papers and Books does not discuss the particular cases and particular situation in the functionning of the pll.
I need your help to understand these undiscussed issues.
Let consider a PLL composed of a PFD, a CP, a Filter, a VCO and a frequency divider.

1- The PFD is used detect the frequency and the phase.
One crucial case not discussed is when the reset signals comes at the same time (or before a short time) with the clock signal that drives the PFD.
In that case, the DFF concerened by this clock signal does not set and the VCO voltage will change in the opposit direction. This phenomenon is repeated undefinetely and VCO Vtune will oscillate.
How can we resolve this problem ?

2- When the PLL locks the VCO Vtune stabilise at Vf. If I have well undestood, the filter is designed using as input informations Vf and the CP's current Icp.
The transfert function of the filter is the Impedance Z(s)=Vf(s)/Icp(s).
If we do the computation we can determine all the caracteristics of our filter in terms of Resistance and capacitances. But when we use our filter inside the pll we should not be surprised if the expected results are not found. In fact that is normal since we ignored the additional Impedance of the VCO input.
How can we determine the VCO input before the design of the filter so that the total impedance Z(s) includes the impeance of the VCO input ?


All your replies and comments are Welcommed.

Regards,
Advares.
 

Re: PLL in depth
 

    AdvaRes

    AdvaRes

    Points: 2
    Helpful Answer Positive Rating
Re: PLL in depth


Thanks jecyhale,

As I said I'm using Gadner book as a reference. I don't need books. Could you please explain briefly these issues.

Thanks.
 

Re: PLL in depth

I am sorry, and I will try to explain after I think about it.

Added after 23 minutes:

AdvaRes said:
Hi members,

I'm using the book of Gadner as a reference to understand how PLL is designed and how works its differents blocks. However when I tried to understand in depth these issues, I noticed that the book as well as the majority of the papers and Books does not discuss the particular cases and particular situation in the functionning of the pll.
I need your help to understand these undiscussed issues.
Let consider a PLL composed of a PFD, a CP, a Filter, a VCO and a frequency divider.


1- The PFD is used detect the frequency and the phase.
One crucial case not discussed is when the reset signals comes at the same time (or before a short time) with the clock signal that drives the PFD.
In that case, the DFF concerened by this clock signal does not set and the VCO voltage will change in the opposit direction. This phenomenon is repeated undefinetely and VCO Vtune will oscillate.
How can we resolve this problem ?

2- When the PLL locks the VCO Vtune stabilise at Vf. If I have well undestood, the filter is designed using as input informations Vf and the CP's current Icp.
The transfert function of the filter is the Impedance Z(s)=Vf(s)/Icp(s).
If we do the computation we can determine all the caracteristics of our filter in terms of Resistance and capacitances. But when we use our filter inside the pll we should not be surprised if the expected results are not found. In fact that is normal since we ignored the additional Impedance of the VCO input.
How can we determine the VCO input before the design of the filter so that the total impedance Z(s) includes the impeance of the VCO input ?


All your replies and comments are Welcommed.

Regards,
Advares.
Click to expand...

Hi, Advares
1, Which is the reset signal? is it the signal after the delay for canceling dead zone? Do you refer to the fig2.11? So far, I haven't met this problem.

2, I think we can ignore the impenance of VCO input, because the bandwidth of PLL is usually less than 1/10000 of VCO frequency.
For example, I design the frequency of VCO is 3GHz, but the bandwidth of PLL is only 100kHz, so the input impedance of VCO is larger than 500kΩ for 100k. it looks like open.
Z=1/jwc=1/(2*pi*100k*1p). (the varactor capacitor is about 1pF)
So, the impedance is very small if the frequency is 3GHz, but as a part of Loop filter, it so big that we can ignore it.

BR
 

    AdvaRes

    AdvaRes

    Points: 2
    Helpful Answer Positive Rating
PLL in depth

Yes jecyhale,
I'm using the third edition of the book.
The Reset is the signal generated to reset the DFF of the PFD when the reference and the feedback clocks rising edge are detected.
 

Re: PLL in depth

The reset signal is generated if both UP and DW are active. That happen a small CLK to Q prop delay after the rising edge. Also the NAND2 having a small delay. So there are minimum active times for UP and DW.

The issue in practice is that the current switches are often slower. So you delay the reset and create longer minimum active times for UP and DW. In that way the currents could settle to near full value and the charge integration over phase difference is linear again.
 

    AdvaRes

    AdvaRes

    Points: 2
    Helpful Answer Positive Rating
Re: PLL in depth

rfsystem said:
The reset signal is generated if both UP and DW are active. That happen a small CLK to Q prop delay after the rising edge. Also the NAND2 having a small delay. So there are minimum active times for UP and DW.

The issue in practice is that the current switches are often slower. So you delay the reset and create longer minimum active times for UP and DW. In that way the currents could settle to near full value and the charge integration over phase difference is linear again.
Click to expand...

Thanks for your reply rfsystem.

I have this problem and I coudnt solve it.

Can you help ?
 

Re: PLL in depth

Could you estimate what is the minimum active time of the PFD and what are the switching times of the current sources.

In practice the ratio should be 2-5.
 

    AdvaRes

    AdvaRes

    Points: 2
    Helpful Answer Positive Rating
PLL in depth

The PFD detects Frequecnies of 500Mhz,
the current source is Ic=2µA
 

Re: PLL in depth

So the reference period is 2ns. If you want to use 80% of that period for phase regulation action, because the minimum active times are lost for operation, the minimum active times should be

400ps

Using the guide ratio 2-5, the current sources should switch within

80-200ps

For a 2uA current source it seems pretty quick. I assume that the VDSAT of the current sources are low, so there are slow and you do not use minimum lenght devices.
 

    AdvaRes

    AdvaRes

    Points: 2
    Helpful Answer Positive Rating
Re: PLL in depth

rfsystem said:
So the reference period is 2ns. If you want to use 80% of that period for phase regulation action, because the minimum active times are lost for operation, the minimum active times should be

400ps

Using the guide ratio 2-5, the current sources should switch within

80-200ps

For a 2uA current source it seems pretty quick. I assume that the VDSAT of the current sources are low, so there are slow and you do not use minimum lenght devices.
Click to expand...


Hi rfsystem,
Do you mean that I should reduce the current ?
I used the minimum width of the transistors. How can I reduce this current to around 0.5µA ?
 

Re: PLL in depth

need more disscution
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top