Sreya39
Junior Member level 2
Verilog coding query
Hi frenz,
i am facing trouble in findinding the biggest number and its position in verilog ....
i am attaching the code with this... any help plzzzzz
module sambig(clock,Enable, corrouti1,corrouti2,corrouti3,corrouti4,corrouti5,dataout) ;
input clock;
input Enable;
input [9:0]corrouti1,corrouti2,corrouti3,corrouti4,corrouti5;
output [9:0] dataout ;
reg [9:0] r1[1:5];
integer i,ADDR,temp=1;
always @(posedge clock) begin
if (Enable) begin
r1[1]= corrouti1;
r1[2]= corrouti2;
r1[3]= corrouti3;
r1[4]= corrouti4;
r1[5]= corrouti5;
end
for (i = 1; i < 4; i=i+1) begin
if (r1 < r1[i+1] )
assign ADDR = i+1;
else
assign ADDR = i;
if (r1[temp]< r1[ADDR])
assign temp = ADDR;
end
end
assign dataout = r1[temp];
endmodule
Hi frenz,
i am facing trouble in findinding the biggest number and its position in verilog ....
i am attaching the code with this... any help plzzzzz
module sambig(clock,Enable, corrouti1,corrouti2,corrouti3,corrouti4,corrouti5,dataout) ;
input clock;
input Enable;
input [9:0]corrouti1,corrouti2,corrouti3,corrouti4,corrouti5;
output [9:0] dataout ;
reg [9:0] r1[1:5];
integer i,ADDR,temp=1;
always @(posedge clock) begin
if (Enable) begin
r1[1]= corrouti1;
r1[2]= corrouti2;
r1[3]= corrouti3;
r1[4]= corrouti4;
r1[5]= corrouti5;
end
for (i = 1; i < 4; i=i+1) begin
if (r1 < r1[i+1] )
assign ADDR = i+1;
else
assign ADDR = i;
if (r1[temp]< r1[ADDR])
assign temp = ADDR;
end
end
assign dataout = r1[temp];
endmodule