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Problem with PLL constructed with VCO

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master_picengineer

master_picengineer

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PLL Construction

Hi all,

I have a VCO of 800 Mhz (800 Mhz is when Vc=1.6V). When I construct the PLL using this VCO the frequency output of the PLL became 780 Mhz (also Vc=1.6 V).
Is that normal ?
Why this happen and Is there any solution to make the pll delivering 800 Mhz signal like the VCO?

Please Help.
 

PLL Construction

what is ur ref freq?
maybe ur Kvco is too large
 
PLL Construction

check for phase detector gain
adjusting it can give ur required results
 
Re: PLL Construction

Thanks everybody,
I tried an experiment: To be sure that this problem is not induced by the PFD or the Freq divider, I connected the Vc directly to the Voltage 1.6 V. Unfortunately I still get a frequency of 780 Mhz.
Please help !
 

PLL Construction

well, i think this means that the divider loading on the VCO is the reason.
 
PLL Construction

Thanks Safwatonline,
It is a divider by 16. Could you please tell me how to resolve the problem ?
Please help.
Thanks so much.
 

PLL Construction

try by disconnecting divider in above diagram circuit
then if problem persists go for VCO change
otherwise divider is loading VCO
 

PLL Construction

try by disconnecting divider in above diagram circuit
then if problem persists go for VCO change
otherwise divider is loading VCO
 
PLL Construction

Thanks ehsanelahimirza,
When I disconnect the divider the VCO is isolate so it works well at 800 Mhz.
Like stated by safwatonline, the problem is due to the divider loading.
Please help me to find solution to this problem.
 

Re: PLL Construction

Hi, if Your divider is realised as digital circuit within chip (FPGA, CPLD,...) check the voltage level of Fout that enters the chip. Maybe it's not appropiate.
 

PLL Construction

Thanks,

The design is done at transistor level.
 

Re: PLL Construction

master_picengineer said:
Like stated by safwatonline, the problem is due to the divider loading.
Please help me to find solution to this problem.
Click to expand...


now i can suggest u a simple and working solution

just use a unity gain OP-AMP configuration

possibly u need 2 op-amps
depend on ur design
 
PLL Construction

Thanks a lot my friend.

Could you please elaborate ehsanelahimirza ?
Should I introduce an OP-Amp between the VCO and the freq divider ?
Can someone sent me some material/shematic of an OP-Amp at transistor level ?

Thanks in advance.
 

Re: PLL Construction

ehsanelahimirza said:
master_picengineer said:
Like stated by safwatonline, the problem is due to the divider loading.
Please help me to find solution to this problem.
Click to expand...


now i can suggest u a simple and working solution

just use a unity gain OP-AMP configuration

possibly u need 2 op-amps
depend on ur design
Click to expand...

Could through more light on this technique ? In conventional PLL I had never saw OP-AM.
And the OP-AM itself have a load and it introduces delay ?
 

Re: PLL Construction

it happened to me for my Clock Data Recovery, it is because of loading capacitance. IMHO, even you put the OPAMP after the VCO, the frequency still the same, maybe the swings are improve or maybe frequency become worse. Actually for design methodology, you need to include the loading capacitance; eg. fan out capacitance, bond pad capacitance, parasitic and etc.

maybe someone have any experienced can give the ideas on this design methodology or design tips.

thanks,
 

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