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Hi,
A port with 50 Ohm resistance can be used as the input noise source, attach it to the input of your circuit, that's all you needed to do in the schematic level,
then choose .noise analysis in the design environment,
set the frequency range you are interested,
and in the "output noise" frame, select output port if you have port in your schematic, if not, select positive voltage node and the negative voltage node,
in the "input noise" frame, select the input port you added to the input of the circuit
that's OK, you can run it now.
After running it, you can directly plot the input refered noise in the "results->directl plot" dialog.
I cannot remember it in hspice very clearly, but I still remember that you can use .noise analysis to get what you want, as to the syntax, you can refer to the design mannual, search it, I am sure that you can get it.
i think like any simulation it is best to add an offset for noise to the final calculation for the given type of chip
its not the best to simulate noise
it causes much unneeded slowing and over calculation and to add it first is daft anyway
as this gives always a runtime view and not a batch view per device charicteristics
hi,all
i have another question that if i use correlated double sampling to reduce the 1/f noise or sc_cmfb to bias the cm output, how to simualte the noise of the circuit.
Hi,
A port with 50 Ohm resistance can be used as the input noise source, attach it to the input of your circuit, that's all you needed to do in the schematic level,
then choose .noise analysis in the design environment,
set the frequency range you are interested,
and in the "output noise" frame, select output port if you have port in your schematic, if not, select positive voltage node and the negative voltage node,
in the "input noise" frame, select the input port you added to the input of the circuit
that's OK, you can run it now.
After running it, you can directly plot the input refered noise in the "results->directl plot" dialog.
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