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Question with Spartan 3 I/O port initialization

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EDA_hg81

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spartan 3 initialization issue

I have used few I/O pins of Spartan 3 for realizing power sequence, the time interval between them is critical.

The problem is when power on the whole system, during initialization time all those I/O ports are driven to high at same time and then all are driven to low.

The problem is above situation is impossible to realize power sequence since all I/O ports are driven to high at same time and will turn on all Mosfet.

How i can fix this ?

Should I connect buffer between FPGA and Mosfet.

Thanks.
 

spartan 3 i/o configuration

There are no way to control I/O until the end of the configuration process, unfortunately. You can use DONE signal to control external devices at startup.

bis
 

    E

    EDA_hg81

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question related to io ports

I plan to connect an inverter between FPGA and Mosfet and use RC delay circuit to

delay the power of the inverter.

I am wondering if the operating voltage of inverter 74LVT04 from 2.7V to 3.6V means 74LVT04 only

can work reliably between this range?

If it is true I can set RC delay circuit to delay 2 second before power of 74LVT04 rearchs 2.5V ?

Maybe this is the way the realize the power sequence.

Do you think it is possible?
 

spartan 3 port delay

If pin HSWAP_EN is low, all the I/O pins will have pull-up resistors (a few kilo-ohms) during configuration.
If pin HSWAP_EN is high, all the I/O pins will float (high-impedance) during configuration.

You could tie HSWAP_EN high to float the I/O pins during configuration, and then install your own weak pull-down resistors to hold the I/O pins low during configuration.

I've never used a 74LVT04.
 

    E

    EDA_hg81

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spartan 3 io rise time

You could tie HSWAP_EN high to float the I/O pins during configuration, and then install your own weak pull-down resistors to hold the I/O pins low during configuration
Click to expand...

On the PCB HSWAP_EN is fixed to high.

Would you explain how I can realize your above idea?

use pulldown attribute of XST ?

Please give me a example.

Thanks
 

spartan iii ports

Anything specified in UCF or VHDL/Verilog/schematic is unknown until after configuration. You will need to add external resistors to weakly pull the lines low or high during power-on and configuration.

If that still leaves power-on sequencing too unpredictable, add power-on counters (for delay) or a power-on state machine to your design.

If it is true I can set RC delay circuit to delay 2 second before power of 74LVT04 rearchs 2.5V ?
Click to expand...
Delays are timed after an event, not before.
 

    E

    EDA_hg81

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external pulldown spartan iii

I used power on counter in my design.

But IO condition during configuration is unpredictable.

I am trying use RC circuit to solve this problem.

I will let you all know the result.

Thanks.
 

delay spartan 3

better method is to use done signal which is provided in device
 

    E

    EDA_hg81

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spartan3 pin state during configuration

One more question,

When power on inverter, the output of inverter is high or low?

should be low right?

Thanks
 

eda board spartan 3 sequence

i thing if ur not giving input to inverter cmos ,and ttl may have different o/p
 

    E

    EDA_hg81

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spartan 3 initialization

Ideally, if the input remains low as the power rises, the output will rise. And if the input rises as the power rises, ideally, the output will remain low. If the input is unpredictable or rises partially, the output can be unpredictable.
 

    E

    EDA_hg81

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hswap_en i/o pins during configuration

If I use RC circuit to enlarge the power rising time to the inverter and the input rising time to inverter follows the I/O rising timing set by FPAG without RC power delay.

What is the result?

Some guy said if use this way the inverter can be damaged.

Thanks.
 

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