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Key indicator for a synthesis run

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cafukarfoo

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I am very interested to know the key indicator for a synthesis run.

As far as i know, we take note of the item below:
1. Slack histogram - to check on the timing performance of the overall design
2. slack report - to check timing for certain critical path
3. Area report - to check the design area after the synthesis
4. formal verification report - to check whether the design is being synthesized correctly.

Am i missing other key indicator?

Really appreciate your important input.
 

Synthesis is a process of GIGO. You can think it may be Good Input Good Output ot Garbage In Garbage Out.

Syntheis is mainly dependent on design constraints. The validity of synthesis is 100% validity of design constraints. QOR report is the initial phase of analysis.

FV report cant guarentee 100% transformation. Thats the reason we run Gate level simulations.

Good to keep posting more concerns about synthesis wrto BackEnd perspective..
 

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    cafukarfoo

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What is the indicator or checklist in the synthesis flow that i can take a look to ensure 100% of my constraint had been taken care?

thanks a lot for your input.
 

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