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Pls help me to check the bias schematic

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tony_wu_ad

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Dear all:

I am new circuit designer. Now my boss give me a schematic about bias. It is very simple, but it is different from schematic from book. The next pic is schematic, the number on schematic is DC point.

I think it is different from book. why the schematic use two PMOS, why the gate of the first PMOS direct connet with D of the second PMOS? I simulate the schematic, the result show that the first PMOS in the trigion.

Pls give me some advice ? Think you ! :D
 

i think this circuit is just a voltage divider.
 

The two PMOS structure in the picture is called "self-cascode" structure. You can refer to the attached paper to study the characteristics of this kind of structure.
 

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    tony_wu_ad

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walker，thank you very much. I have learn the document that you give, it is very good.Thank you!
 

HI
If W/L of two transistors are equal, two transistors act as a transistor with W/2L.
so for a givven current we have higher Vgs and then Lower Vg.
regards
 

    T

    tony_wu_ad

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hr_rezaee said:
HI
If W/L of two transistors are equal, two transistors act as a transistor with W/2L.
so for a givven current we have higher Vgs and then Lower Vg.
regards
Click to expand...

hr_rezaee, the W/L of two transistors are equal.
I see the two PMOS, yet they can see as one PMOS with W/2L.
Think you :D
 

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