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Input delays to the combo logic and output delays are specified w.r.t a clock, which need not be in the design. This clock is created in the constraints and is not mapped to any pin/port in the logic. hence the name virtual clock
Its not compulsary to use a virtual clock for constraining the input/output ports...u can also use set_max_delay and set_min_delay constraints for u r combo logic block.
set_max_delay is higher level of timing constrains ...
in this case u r suming up whole delay into one command..
but when u use input delay w.r.t clock combo delay is not taken ..
PS:correct me ...if i am wrong
check this article on static timing analysis
you will really understand about virtual clocks concept and why it is all needed to constrain the external world
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