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How to design an opamp with these specifications?

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cadenceucy

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op amp design HELP

I have to design Differential input (Vin-&Vin+) operational amplifier with input
I bias for external biasing, input SelectExtbias and single ended output.
With the following specs:

OLDC Gain>75db
Unity gain Bandwidth>100Mhz
Phase-Margin>45db
Input referred offset <4mV
Power Supply Rejection at 1 KHz >40db
Input range: 0.5V<Vin<1.5v
Output range: 0.5V<Vout<1.5v
Vdd=2.5V =+/-25%
Iref External 10uA+/-20%
Slew Rate (unloaded)>100V/us
Does anybody know how I will start?
Thanks
 

op amp design HELP

Yea -- try to get an idea of what topology your design will have to be. For example, your input/output ranges might eliminate some topologies..You might need to use gain boosting or some other techniques to meet the gain spec... etc..
 

    C

    cadenceucy

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op amp design HELP

A first thought will be
DC gain and GBW => fd
45 PM => fnd = GBW
In/out range and Vdd => folded cascode
then read Allen&holberg's book and follow
the procedure
 

    C

    cadenceucy

    Points: 2
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op amp design HELP

agree, try look at the books
 

Re: op amp design HELP

lladnar23 said:
Yea -- try to get an idea of what topology your design will have to be. For example, your input/output ranges might eliminate some topologies..You might need to use gain boosting or some other techniques to meet the gain spec... etc..
Click to expand...

can u give me an example
 

Re: op amp design HELP

Thanks for all post.

Finally I used the two state op amp topology. I have near to 80 db DC Gain and 90 MHz unity gain bandwidth. But the other specs are not achieved, please help me. I attached my design
 

op amp design HELP

second stage use cascode can increase the PSRR and
gain . the over drive voltage you can use 0.2v.
you should use miller cap compensation between first stage and second stage to improve the phase margin.
you work current should meet the slew rate(where is you load Cap).if the ICMR is not achieved ,youshould use the folded cascode structure.
 

    C

    cadenceucy

    Points: 2
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Re: op amp design HELP

Thanks for all post.
Finally I use this configuration using pmos transistor as current mirror. I achieved almost a lot of specifications except an important one. When vdd is below 2.4 v and vin raised from 1.1V to 1.5 V I lose the Gain. Is any trick to do operate with 2v vdd and 1.5 v Vin??
Please HELP

Thanks.
 

op amp design HELP

change your input differential pairs to NMOS, it will ok
 

op amp design HELP

agree with rfzheng and you can use folded cascode structure
 

Re: op amp design HELP

pwell?
why use nmos better?
 

op amp design HELP

yes, i feel folded cascode structure will solve ur problem
 

Re: op amp design HELP

I have the same question, too

what is the reason to use NMOS diff pair rather than PMOS diff pair?
 

Re: op amp design HELP

KianChang said:
I have the same question, too

what is the reason to use NMOS diff pair rather than PMOS diff pair?
Click to expand...

This can be because of your ICMR (input common mode range). Deciding to use NMOS or PMOS can impact your meeting this specification because of the different vdsat drops from rail to input in the two cases (PMOS and NMOS).

This attachment is from Allen and Holdberg, it has some good information on how to design to meet specs.
 

    C

    cadenceucy

    Points: 2
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Re: op amp design HELP

read Allen 's book-Analog IC Design
 

Re: op amp design HELP

follow the following book

cmos_analog_circuit_design by allen & holberg
 

Re: op amp design HELP

we have almost the same spec requirement in the project this semester of AIC.
Am I know you?
 

Re: op amp design HELP

follow the following book
cmos_analog_circuit_design by allen & holberg
Click to expand...

Where Can I download the book?
 

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