Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Need Help: PLL for 50 Hz

Status
Not open for further replies.

emreozer

Member level 2
Joined
Nov 13, 2006
Messages
45
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,286
Location
Istanbul - Turkey
Activity points
1,572
50hz pll

Hi everyone

I must design a PLL for 50 Hz. Anybody advise me a circuit?

Thanks
 

circuit of application with nte864

50 Hz is very slow. Check Razavi's book for the schematics.
 

    emreozer

    Points: 2
    Helpful Answer Positive Rating
pll mit 2206

Yes, I know 50 Hz is very ow frequency, but this is special application.

Could you sedn me Razavi's book link?

Thanks
 

xr-2206 pll

check the possibility of using a digital PLL as well
 

    emreozer

    Points: 2
    Helpful Answer Positive Rating
pll loop 50hz software

Design of Analog CMOS Integrated Circuits - Behzad Razavi. It has a good chapter on PLLs. I believe the main difference between an analog PLL and a digital PLL will be in the design of the voltage controlled oscillator.
 

    emreozer

    Points: 2
    Helpful Answer Positive Rating
need of pll

The problem I see is that you need reference frq. to be min 10x lover to satisfy all the requirements for PLL loop stability. Remember - Razavi and comp do neglect tons of stuff because the analysis would be way too copmlicated.
So a - get the reference freq
b - design vco running at least 10x higher
c- fight with filter - if it is on chip - sorry no way
 

    emreozer

    Points: 2
    Helpful Answer Positive Rating
pll for 50hz

Teddy said:
The problem I see is that you need reference frq. to be min 10x lover to satisfy all the requirements for PLL loop stability. Remember - Razavi and comp do neglect tons of stuff because the analysis would be way too copmlicated.
So a - get the reference freq
b - design vco running at least 10x higher
c- fight with filter - if it is on chip - sorry no way

Hello Teddy, what is the "reference frequency"? Will that be the from the signal going into the PFD, in this case 50 Hz? Also, about the reference frequency being at least 10x lower to satisfy loop stability ... can you give some book or journal references about this? Thanks!
 

    emreozer

    Points: 2
    Helpful Answer Positive Rating
I want to regenerate 50 Hz, so I want to use PLL.

Anybody tell me another signal regeration method?

thanks
 

Yes it is going to PFD
Make VCo at higher frequency and divide it down to 50 Hz
Use razavi's book or the free - PLL Performance, Simulation, and Design - by Dean Banerjee - it is here somewhere. There you learn what to dd
But I tell you 50Hz - hope this is going to be from discretes....
 

    emreozer

    Points: 2
    Helpful Answer Positive Rating
Did you check CD4046 or equivalent ic ?
 

    emreozer

    Points: 2
    Helpful Answer Positive Rating
you can use pll ic or a flip flop this will not be affected by the low frequency
 

    emreozer

    Points: 2
    Helpful Answer Positive Rating
Thanks for all explanations but the output waveform of PLL must be sinusoidal wave form, not square wave.

anybody know PLL for 50 Hz ( has sinusoidal output)?
 

Hi again

Can I design a PLL by using NTE864 or XR-2206 (Waveform Generator)?

Anybody has application note about NTE864 or XR-2206 or any waveform generator circut schema?

Anybody did it before?

Thanks
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top