Dual pins of SPartan3 FPGA(TQ144 package)

1.Is it possible to provide VCCO_4 and VCCO_5 as 3.3V , or is it compulsory to give both these as 2.5V since it is used in configuration and other dedicated configuration pins are driven from VCCAUX which is 2.5V?
2.It is given in Spartan 3 datasheet that certain pins in Banks 4 and 5 can be used as Dual function pins.If we are using these pins in configruation and also as I/O pins how should we provide the connection with these pins.
Is it enough to simply give two connection from each dual fumction pin, if so how will the fpga differentiate between configuration and other signals.Should some switching arrangement be provided for this.?
Does the VCCO_4 and VCCO_5 voltage of the fpga depends on the VCCO and VCCJ of the parallel platform flash PROM interfaced to it?

I would suggest reading the app notes and searching the knowledge base at:

www.support.xilinx.com

After doing that call the Tech Line and explain exactly how you want to power the device. I have been burnt in the past by the datasheet not exactly matching the parts in this regard. Due to this fact, we not use the JTAG programming interface only. This is powered from VCC AUX and is not subject to other banking requirements, at least on the parts we are currently using.

For dual function pins, you should use switches to isolate the two functions. For some requirements, you may get away with a simple parallel connection. However, in general, you want a switch to insure that the two functions remain separate. Look at the Maxim or Analog device web site and you will find silicon switch packages in a number of configurations. Because of the capacitance of the switch, you will not get full bandwidth from these signals. Therefore, you need to limit these to functions that are control or support functions. Either control the switches with an external piece of logic or processor, or make sure that the switch defaults to the state that allow configuration to occur. Otherwise you end up with the chicken and egg problem, of you cannot control the switches until you program the FPGA and you cannot program the FPGA until you get switch control.
With regard to the VCCO and PROM requirements, there is an app note on making VCC2.5 banks to be 3.3V tolerant by adding series current limiting resistors. Therefore, 3.3V PROMs can be used with this technique. Many PROMs and EEPROMs work over a very wide range. Therefore, you may be to run the PROM on 2.5V directly also. Check the PROMs datasheet for its VCC range.

Thanks, Can you make it some more simple?
We dnt have space to keep a processor to control the switch.
During configuration these dual pins should act as dedicated pins right?
Can you please suggest a simple way rather than going for controlling the switch?

Yes, you can have 3.3 Vcc on all banks but you must have a 2.5V rail for Vaux. Some pins may need serial current limiting resistors. Please take a look at User Guide 332 and Figures 3-5 in Application note XAPP453; I think this exactly answers your question on how you want to configure the interconnect... Actually, you may want to take a look at the Spartan-3A family; Vaux can either be 2.5 or 3.3V, so you can save a rail in this new family and there is a TQ144 available.

You do not need a processor to control the switches. You can use either other external logic or the FPGA itself. For example, assume that you choose a SPDT switch. And also assume that the switch control line is active HIGH. You want to connect the common switch terminal to the FPGA and the NC, or normally closed terminal to the configuration circuit. The NO, or normally open terminal is connected to the circuit used after configuration. The control terminal is connected to an FPGA pin AND connected via a resistor to GND. Before the FPGA is programmed the control pin will be LOW due to the resistor since the FPGA defaults to all inputs when blank. After programming, the FPGA drives a logic HIGH on the control pin and switches it the other way.
You do not even need any internal logic to do this as you can program the I/O to drive a HIGH after the programming sequence is complete. Since you are not toggling these switches during normal operation. You can wire all the switch control lines in parallel and connect them back to a single FPGA pin.
If you want to get really tricky, you could even use the DONE pin of the FPGA as the control line. This open-collector output is LOW during the blank or programming in progress state and goes open when programming is complete. All you have to add is the pullup resistor.

I am still a little confused.
In my application Fpga's bank 4 and 5 are having dual pins which are first used in configuration mode(fpga interfaced to Platform flash PROM).
And an LED is connected to the same dual pin.
Once the configuration is over, DONE pin gets high and acts as I/O pin.
So my doubt is
1) do we have to connect a switch , to select configuration pins or LED?
2)Whether the configuration takes place first?. Will the switch me in that state first(is that its default state?
3)How does it switches to the LED circuit then?(automatically after configuartion is over?)
4)If i want the configuration to takes place first do i have to connect it as the default state?aand how does it changes from the default state?(by means of any program from fpga?)
For ex take the case of ADG779 switch.
Can we connect the IN control input to DONE?and s1 to configuration pin and s2 to LED?
So when the fpga is switched on will it take the configuration pin as the first ?and s2 aft that?

Is there any other way than the switch to isolate two circuits?As we dnt have much space to place switch. Or can you suggest a smaller dimension switch?

To connect the switch you mentioned, connect "D" to the FPGA, connect "S1" to the configuration PROM, and connect "S2" to the LED. The "IN" terminal would be connected to the FPGA "DONE" pin and this pin would be pulled up to VCCAUX via a resistor.
On power-up, DONE is low. This insures that the switch is in the S1 position. (Be careful of the datasheet, the switch is drawn with a '1' on the "IN" pin.) At the very end of the programming cycle, the FPGA releases the DONE pin and the pull-up resistor pulls the pin high which switches you over to the S2 position. After programming, if you toggle the "PROG" pin of the FPGA, then "DONE" will again go low and allow you to reprogram the device.
Now, if you are only using LEDs on the dual use pins, you have a special case. The pin will only be an output and will be a very low bandwidth output. Therefore, it may be possible to do a parallel connection and eliminate the switch. The criteria are:
1. Is the pin on the PROM an output or an input? If it is an output, does the PROM tristate the output when programming is completed? If so, you may be able to parallel the LED output. The remaining concern on an output is that the LED does not load down the signal levels and cause programming to fail. If the PROM pin is an output that does NOT tristate, then you need to switch. Otherwise, you will have a "bus contention" on that pin.
2. If the pin is an input to the configuration PROM, what will the effect of toggling this pin after programming has completed? If you can be sure that the PROM will ignore the toggling after programming, then you can most likely toggle the pin without a problem.

Do you have a demo board? Since you are talking about very low bandwidth signals, it may be easiest just to solder some wires to a demo board using a similar PROM and do some experiments. If you have a first revision of your design, this could be used too. The PROM is often an easy point to solder to as the leads are bigger than the BGA vias.

Finally, are you so pin limited on the FPGA that no other pins are available for the LED? Generally, people do not attempt to dual use the pins in the same design. For example, if the design is programming via JTAG, they will use these pins for other purposes. If the design is using a PROM, they generally dedicate the pin to the PROM function. For high speed designs, we like to keep the utilization at less than 80%. Trying to get larger than mid 90% will very often cause place and route problems for speed critical nets.

Finally, if you are using a parallel PROM, review the configuration literature and consider switching to a serial output PROM, this should free up some pins for you to use.

Re: Dual pins of SPartan3 FPGA(TQ144 package)plz help...

Hi,
When we used TQ144 package (FPGA interfaced to platform flash PROM) , even after using the dual purpose pins; I/o pins are not sufficient.We have 9 more connections I/o pins left unconnected.
Cant change PROM ,as parallel PROM is faster. Cant change to any other fpga package..;as pq package is having height and bga soldering is costly

Will the use of microcontroller+PROM(instead of platform flash PROM) save pins.? If so how it is implemented?

Can anyone please suggest a better way?

I can think of only two choices: Either requires that you make some concessions with your design criteria.

1. Use a serial PROM. While slower, it is only used at power-up to configure the FPGA. I think the wait time is insignificant when looking at the overall use of any device.

2. Find some non-critical outputs that can be moved to a port expander. For example, the MAX7321 is an I2C to eight output open drain driver. Lots of other serial interface drivers exist. These can often be either connected in a daisy-chain or in parallel. Therefore, you use three or four pins to control 32 or more outputs. The limitation is that to change one of these outputs, you have to clock it out serially. Therefore, it is not speed critical. However, for LEDs or control lines that only configure other devices and do not change often, it is fine. While I mention outputs. I you can do low speed inputs as well with chips like the PCF8574 from Philips. This would work for stuff like switches, etc. The cost of this type of port expander is that you have to write a state machine to run the I2C interface.

I do not think a microcontroller/PROM solution really adds anything to your design. The advantage of that approach is then you have several different FPGA bit files. The microcontroller allows different FPGAs to be loaded for different purposes. However, the interface is usually serial to the PROM and therefore is slower than the parallel interface.

Changing to serial PROM is not preffered...
And the IC having I2c serial interface. It is supported by software program which will increase the cost..
Is there any other Ic like that which is not software driven...

Ok,

We have a saying, "What you are trying to do is put 10 pounds of 'stuff' in a 5 pound box." To do that requires lots of work. (We also use a much more vugar word for 'stuff'.)

There are many interface type of ICs. If you do not like I2C, other simpler intefaces exist. For example, look at the datasheet for the Allegro 6276.

**broken link removed**

This IC is designed to drive LEDs and has a simple serial interface. You place the data on the input pin one bit at a time and then apply a clock pulse. After clocking in all the data, you apply a latch enable. This can be handled by a simple state machine within the FPGA with no software overhead.
For example:

State "1" would copy the output byte into a temporary register. Bit0 of the temporary register is the output data pin of the FPGA.
State "2" would issue a rising clock edge.
State "3" would issue a falling clock edge.
State "4" would shift the data downward in the temporary register.
State "5" would count how many shifts have occurred an either loop back to State "2" or continue to State "6".
State "6" would pulse the Latch Enable.
State "7" would return to State "1".

This simple example state machine would continually loop around clocking new data to the LEDs. If you want to be more complex, you can compare the present output byte with the last byte you clocked out and only clock out data when a change was detected. In either case, it is not software driven, it is firmware driven by a state machine within the FPGA.
The Allegro device is only an example. Maxim, Analog Devices, TI and several other vendors make similar chips. Each vendor has its own unique properties. Just select the chips that fit your needs.

Thanks a lot for your suggestion.
The pin to which i have to connect this type of IC to drive an LED in TQ144 package is a configuration pin(eg-IO_L30P_4/D3pin).So after configuration wont this pin automatically drive LED? Do we use the IC u suggested?
More than that there are other critical signals other than driving LEDS to be connected to IO pins. so I think we should avoid some less critical signals which is the only better way.