Question about Verilog RTL syntax

Izzit any different between below case?


Case 1:
always @(posedge clk_i)
begin
game_a_0 <= game_a_i;
game_b_1 <= game_b_i;
end


Case 2:
always @(posedge clk_i)
game_a_0 <= game_a_i;
always @(posedge clk_i)
game_b_1 <= game_b_i;

Will case 2 be better for synthesis tools to interpret?!


Any comments??!!

rtl syntax

These two pieces of code are really syntacially the same. To Verilog, the begin and end are the same as the "curly brace" to a C program. The compiler understands that everything between the begin and end occur at your clock transition.

Case #2 is sometimes viewed as bad coding style. The reason is it easily introduces errors when modified. For example, let us say I want to add a game_c set of flops. If I am careless, then I just paste them in as such:

always @(posedge clk_i)
game_a_0 <= game_a_i;
game_c_0 <= game_c_i;
always @(posedge clk_i)
game_b_1 <= game_b_i;

While you might think that the clock edge constraint would apply to game_c, it does not. The signal game_c_0 would be interpreted as combinatorial by the compiler. The "always @(posedge clk_i)" works just like an if statement in C. When you use an if statement in C, it only apply to the very next statement UNLESS you use the compound statement braces.
Therefore, it is better for readability and fewer errors when modifying to use your "CASE #1".

Re: Verilog RTL syntax

From synthesis point of view...the hardware generated by the tool for the two cases are identical...

i suggest to use case1, since u have all the operations based on the same clock, there is no need to put more always@

Regards,
dcreddy

Verilog RTL syntax

I think it is no difference to synthesis tool.
But i am prefer :

always @( posedge clk_i )
begin
game_a_0 <= game_a_i;
end

always @( posedge clk_i )
begin
game_b_1 <= game_b_i;
end

Only one variable is assigned in one always block