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Simulation of a charge pump for a VCO for PLL

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dhasmana

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Hello,

I have to simulate a charge pump circuit used in the VCO of a PLL.I have the PFD and the charge pump schematic only.How can I simulate it as a stand alone circuit?What inputs I should give at the Reference and Feedback inputs of the PFD (Phase freq. detector?). How can I find out the phase error?

Regards.
 

u need to simulate the average output current of the charge pump with the phase difference between the Fref and Ffeedback

also u need to do it with frequency difference as well

khouly
 

    D

    dhasmana

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Hi,
Thanks for the reply.
This is an open loop system with the PFD folowed by the CP.If i give the Ref. clk and the feedback clk with some phase diff, that will correspond to a particular value of the CP out voltage (Vcontrol) in steady state.
How do I know that when the PLL will lock (I do not have whole PLL or VCO ckt ), what will be the phase error?DO I need to know the value of Vcontrol for the locked loop (this will depend on the VCO characteristics and also the divider).

The unit of max. allowed Static phase error is in pS.That is an absolute quantity.At what ref. freq. will the static phase error be max?At max ref. freq. or min. ref. freq?Is SPE (static ph. err) dependent on freq?

How can I simulate integrated phase noise upto 30KHz?

Please help.
Regards.
Dhasmana.
 

You don't need to know the value of Vcontrol. The value of Vcont is a variable, and it varies until the loop is stable. You can just simulate the PFD, CP and LPF without VCO or dividers. What freq does not matter.
 

    D

    dhasmana

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How can I find out the static phase error?
What inputs should I give to the two inputs of the PFD, one clk and one feedback clk.?

Regards.

Added after 3 minutes:

The phase diff. between the clk and the feedback clk. when the average CP current (current into the cap) is zero will be the total static phase error?

Regards,
Dhasmana.
 

You need to do at least three cases for PFD+CP in transient simulation
(1) REFCLK > FBCLK (frequency & phase)
(2) FBCLK < REFCLK (frequency & phase)
(3) REFCLK=FBCLK

Put the real Loop filter after CP to check the voltage for the three cases.
 

    D

    dhasmana

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You also need to check the following things

1-Up and Down currents are the same
2-Look for the dead zone-What happens when the two inputs to the PFD are almost in phase? Run simulaitons where the two inputs are +/- 10% in Sync. For example, if you have a 10 MHz reference signal, have the two signals offset by -10nSec, and change the offset by 1 nSec, up to 10 nSec. You'll see that even if the two signal's are not aligned, there will be no output. The range of offsets for this is called the dead zone.
3-Check charge pump linearity-sweep the offset from +/- 2pi, and plot the charge pump output charge (Integrate the charge pump output over the period) and make sure it's reasonably linear.

Dave
 

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    dhasmana

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Hi,
why should sweep the offset from +/-2pi?Can you explain more?
Thanks a lot.

RFDave said:
You also need to check the following things

1-Up and Down currents are the same
2-Look for the dead zone-What happens when the two inputs to the PFD are almost in phase? Run simulaitons where the two inputs are +/- 10% in Sync. For example, if you have a 10 MHz reference signal, have the two signals offset by -10nSec, and change the offset by 1 nSec, up to 10 nSec. You'll see that even if the two signal's are not aligned, there will be no output. The range of offsets for this is called the dead zone.
3-Check charge pump linearity-sweep the offset from +/- 2pi, and plot the charge pump output charge (Integrate the charge pump output over the period) and make sure it's reasonably linear.

Dave
Click to expand...
 

Sorry, that should be +/- pi. If you have 2 square waves, with a 50% duty cycle, then they can be in phase, with the rising edges at the same instant, or 180 degrees out of phase, where the rising edge of one is at the same instant as the falling edge of the other. Start at at one offset, and sweep towards the other.

While you are at it, you should probably make sure that at large frequency offsets, your charge pump/PFD behaves in such a way as to drive the loop towards lock.

You also might want to play around with the duty cycle of the input signals, to make sure that things work on the rising edges only.

Dave
 
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    dhasmana

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    benW

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Hi !!

Thanks for your interest and support by answering.

What is the meaning of integrated phase noise?
How can I simulate for integrated phase noise upto say 10MHz?

I understand that I can vary the phase diff. between the ref clk and the FB clk. by doing different transient simulations for different phase deifference.BUT how can I sweep the phase difference (offset) in a single simulation?

RFDave wrote:>>>>>"Start at at one offset, and sweep towards the other. "
How can I do this?Please explain.

Regards,
Dhasmana.
 

Hi:

Integrated phase noise is, as you would expect, the integral of the phase noise. Google for spreadsheets that go through the details. You need an upper and lower frequency bound to integrate over. One way would be to export your phase noise plots to a spreadsheet format and do the integration in a spreadsheet.

you may need to do multiple simulations, one for each time/phase offset that you plan to simulate. The simulator tool detail's are left as an exercise for the student.



Dave
 

Hi,
You can give freclk and fdbackclk with a fixed phase difference and have the same frequency, and you should connect a cap at the charge pump output, at simulation, you will find the voltage in the cap will charge up if Freclk > Fdbackclk, and voltage in the cap will charge down if Freclk< Fdbackclk.
if fdbaclk and fredclk has the same frequcency and phase, the voltage at cap will not vary.


BR
crossbow
 

I just arrived at the equation of static phase error (SPE)

delta phi (SPE) = Ierr/Icp* (T)
Where Ierr is the error current due to charge pump, Icp = charge pump limb current and T = Time period in seconds.

This eqn. gives the SPE in Seconds (time).

This means SPE is proportional to the time period of the ref. clk.

If in a technology, the existing design has SPE = x pico seconds at Y Mega hertz,
is it possible/realistic to get a SPE of x pico seconds for Y kilo hertz, I mean a freq. 1000 times less.Does it seems possible?
Comments are welcome.
Regards.
 

Hello,

What is the static phase error due to the PFD (phase freq. detector)?
Should it be proportional to the average shoot through current through the chargepump because of the min. reset pulses?Any thoughts/ideas?

Regards,
Dhasmana.

Added after 44 minutes:

Hello,

Are all the components of SPE (static phase error) like due to CP, due to PFD, due to CP current mismatch etc all additive algebraically?I guess it should be so.. please share your thoughts.

Regards,
Dhasmana
 

You have to simulate the Charge Pump Ckt and plot the average output current of the charge pump (Icp)Vs phase difference(Phy) between the FREF and FEEDBACK .There are many lectures on CP.Best paper for CP is Voughan Rhee`s paper.
 

dhasmana said:
Hello,

I have to simulate a charge pump circuit used in the VCO of a PLL.I have the PFD and the charge pump schematic only.How can I simulate it as a stand alone circuit?What inputs I should give at the Reference and Feedback inputs of the PFD (Phase freq. detector?). How can I find out the phase error?

Regards.
Click to expand...

you simulate by simulink and serenade software
 

sandip_micro said:
You have to simulate the Charge Pump Ckt and plot the average output current of the charge pump (Icp)Vs phase difference(Phy) between the FREF and FEEDBACK .There are many lectures on CP.Best paper for CP is Voughan Rhee`s paper.
Click to expand...

can u please upload that paer or give the link for paer.
 

can the person who posted this msg or someone else send me some schematics of charge pumps (preferably with filters) with description. i m doing a project on PLL.
 

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