Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
To be precise, if you do multi-finger layout, you increase the number of poly ends extension from diffusion and this increase the overlap parasitic cap, so you finally increase the gate parasitic cap to diffusion. Also, you increase poly to substrate cap as you have more gate area extension outside diffusion
Sharing drain/source diffusion, you reduce the drain/source area to substrate and thus reduce the drain/source cap to substrate.
To be precise, if you do multi-finger layout, you increase the number of poly ends extension from diffusion and this increase the overlap parasitic cap, so you finally increase the gate parasitic cap to diffusion. Also, you increase poly to substrate cap as you have more gate area extension outside diffusion
Sharing drain/source diffusion, you reduce the drain/source area to substrate and thus reduce the drain/source cap to substrate.
I agree with you, i have do a comparison for multifinger and single transistor and i get a bigger parasitic cap in multifinger transistor. so, is there other way to keep parasitic cap low besides doing single transistor? because there is a very big transistor in my circuit that i can't design it in single transistor because it will increase parasitic resistance. that will cause my circuit became noisy. i want to design a low noise circuit. thank you.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
